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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor ADSP-BF534/adsp-bf536/adsp-bf537 rev. i information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. features up to 600 mhz high performance blackfin processor three 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring wide range of operating voltages (see operating conditions on page 24 ) qualified for automotive applications (see automotive prod- ucts on page 67 ) programmable on-chip voltage regulator 182-ball and 208-ball csp_bga packages memory up to 132k bytes of on-chip memory instruction sram/cache and instruction sram data sram/cache plus additional dedicated data sram scratchpad sram (see table 1 on page 3 for available memory configurations) external memory controller wi th glueless support for sdram and asynchronous 8-bit and 16-bit memories flexible booting options from external flash, spi and twi memory or from spi, twi, and uart host devices memory management unit providing memory protection peripherals ieee 802.3-compliant 10/100 ethernet mac (adsp-bf536 and adsp-bf537 only) controller area network (can) 2.0b interface parallel peripheral interface (ppi), supporting itu-r 656 video data formats 2 dual-channel, fu ll-duplex synchronous serial ports (sports), supporting 8 stereo i 2 s channels 12 peripheral dmas, 2 mastered by the ethernet mac 2 memory-to-memory dmas with external request lines event handler with 32 interrupt inputs serial peripheral interface (spi) compatible 2 uarts with irda support 2-wire interface (twi) controller eight 32-bit timer/counte rs with pwm support real-time clock (rtc) and watchdog timer 32-bit core timer 48 general-purpose i/os (gpios), 8 with high current drivers on-chip pll capable of frequency multiplication debug/jtag interface figure 1. functional block diagram sport0 can voltage regulator port j gpio port h gpio port g gpio port f jtag test and emulation peripheral access bus watchdog timer rtc twi sport1 ppi spi timer7-0 ethernet mac (see table 1) boot rom dma external bus interrupt controller dma controller l1 data memory l1 instruction memory 16 dma core bus external access bus external port flash, sdram control b uart0-1
rev. i | page 2 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 table of contents general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 blackfin processor peripherals ................................. 3 blackfin processor core .......................................... 4 memory architecture ............................................ 5 dma controllers .................................................. 8 real-time clock ................................................... 9 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) .......................................... 10 serial peripheral interface (spi) port ....................... 10 uart ports ...................................................... 10 controller area network (can) ............................ 11 twi controller interface ...................................... 11 10/100 ethernet mac .......................................... 11 ports ................................................................ 12 parallel peripheral interface (ppi) ........................... 12 dynamic power management ................................ 13 voltage regulation .............................................. 14 clock signals ..................................................... 15 booting modes ................................................... 16 instruction set description ................................... 17 development tools .............................................. 17 designing an emulator-compa tible processor board ... 18 related documents .............................................. 19 related signal chains ........................................... 19 pin descriptions .................................................... 20 specifications ........................................................ 24 operating conditions ........................................... 24 electrical characteristics ....................................... 26 absolute maximum ratings ................................... 30 esd sensitivity ................................................... 30 package information ............................................ 30 timing specifications ........................................... 31 output drive currents ......................................... 51 test conditions .................................................. 53 thermal characteristics ........................................ 57 182-ball csp_bga ball assignment .. ......................... 58 208-ball csp_bga ball assignment .. ......................... 61 outline dimensions ................................................ 64 surface-mount design .......................................... 66 automotive products .............................................. 67 ordering guide ..................................................... 68 revision history 7 /10rev. h to rev. i corrected all document errata. replaced incorrect figure 5 , voltage regulator circuit ... 14 replaced incorrect figure 13 , external port bus request and grant cycle timing ................................................ 34 to view product/process change notifications (pcns) related to this data sheet revision, please visit the processors product page on the www.analog.com website and use the view pcn link.
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 3 of 68 | july 2010 general description the ADSP-BF534/adsp-bf536/ad sp-bf537 processors are members of the blackfin ? family of products, incorporating the analog devices, inc./intel micr o signal architecture (msa). blackfin processors combine a dual-mac, state-of-the-art sig- nal processing engine, the advant ages of a clean, orthogonal risc-like microprocessor instruct ion set, and single-instruc- tion, multiple-data (simd) multimed ia capabilities into a single instruction-set architecture. the ADSP-BF534/adsp-bf536/ad sp-bf537 processors are completely code and pin compat ible. they differ only with respect to their performance, on -chip memory, and presence of the ethernet mac module. specif ic performance, memory, and feature configurations are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, the blackfin processo rs are the platform of choice for next-generation applications that require risc-like pro- grammability, multimedia suppo rt, and leading-edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of oper ation to significantly lower overall power consumption. this capability can result in a substantial reduc- tion in power consum ption, compared with just varying the frequency of operation. this a llows longer battery life for portable appliances. system integration the blackfin processor is a highly integrated system-on-a-chip solution for the next generati on of embedded network-con- nected applications. by combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. the system peripherals include an ieee-compliant 802.3 10/100 ethernet mac (adsp-bf536 and adsp-bf537 only), a can 2.0b controller, a twi controller, two uart ports, an spi port, tw o serial ports (sports), nine general-purpose 32-bit timers (eight with pwm capability), a real-time clock, a watchdog timer, and a parallel peripheral interface (ppi). blackfin processor peripherals the ADSP-BF534/adsp-bf536/a dsp-bf537 processors con- tain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configura- tion as well as excellent overall system performance (see figure 1 ). the processors contain dedicated network communi- cation modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or extern al sources, and power manage- ment control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. all of the peripherals, except for the general-purpose i/o, can, twi, real-time clock, and timers, are supported by a flexible dma structure. there are also separate memory dma channels dedicated to data transfers be tween the processors various memory spaces, including external sdram and asynchronous memory. multiple on-chip buse s running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. the blackfin processors include an on-chip voltage regulator in support of the processors dyna mic power management capabil- ity. the voltage regulator provides a range of core voltage levels when supplied from v ddext . the voltage regulator can be bypassed at the users discretion. table 1. processor comparison features ADSP-BF534 adsp-bf536 adsp-bf537 ethernet mac 1 1 can 1 1 1 twi 1 1 1 sports 2 2 2 uarts 2 2 2 spi 1 1 1 gp timers 8 8 8 watchdog timers 1 1 1 rtc 1 1 1 parallel peripheral interface 1 1 1 gpios 48 48 48 memory configuration l1 instruction sram/cache 16k bytes 16k bytes 16k bytes l1 instruction sram 48k bytes 48k bytes 48k bytes l1 data sram/cache 32k bytes 32k bytes 32k bytes l1 data sram 32k bytes 32k bytes l1 scratchpad 4k bytes 4k bytes 4k bytes l3 boot rom 2k bytes 2k bytes 2k bytes maximum speed grade 500 mhz 400 mhz 600 mhz package options: csp_bga csp_bga 208-ball 182-ball 208-ball 182-ball 208-ball 182-ball
rev. i | page 4 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 blackfin processor core as shown in figure 2 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contains eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates, and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 5 of 68 | july 2010 the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the ADSP-BF534/adsp-bf536/ad sp-bf537 processors view memory as a single unified 4g byte address space, using 32-bit addresses. all resources, includ ing internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. th e memory portions of this address space are arranged in a hi erarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or sram, and larger, lower cost, and performance off-chip memory systems. (see figure 3 ). the on-chip l1 memory system is the highest performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 516m bytes of physical memory. the memory dma controller prov ides high bandwidth data- movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the ADSP-BF534/adsp-bf536/a dsp-bf537 processors have three blocks of on-chip memory providing high-bandwidth access to the core. the first block is the l1 instruction memory, consisting of 64k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of up to two banks of up to 32k bytes each. each memory bank is configurable, offering both cache and sram functional- ity. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram, which runs at the same speed as the l1 memories, but is only accessible as data sram, and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the pc133-compliant sdram cont roller can be programmed to interface to up to 128m bytes of sdram. a separate row can be open for each sdram internal bank, and the sdram con- troller supports up to 4 inte rnal sdram banks, improving overall performance. the asynchronous memory cont roller can be programmed to control up to four banks of devi ces with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguo us if each is fully populated with 1m byte of memory. i/o memory space the ADSP-BF534/adsp-bf536/a dsp-bf537 processors do not define a separate i/o sp ace. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the to p of the 4g byte address space. these are separated into two sma ller blocks, one which contains the control mmrs for all core functions, and the other which contains the registers needed fo r setup and control of the on- chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on- chip peripherals.
rev. i | page 6 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 booting the blackfin processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. if the blackfin processor is configured to boot from boot rom mem- ory space, the processor starts executing from the on-chip boot rom. for more information, see booting modes on page 16 . event handling the event controller on the blackf in processor handles all asyn- chronous and synchronous even ts to the processor. the blackfin processor provides even t handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a higher priority ev ent takes precedence over servic- ing of a lower priority event. the controller provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to comp lete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the blackfin processor event cont roller consists of two stages: the core event controller (cec) and the system interrupt con- troller (sic). the core event controller works wi th the system interrupt controller to prioritize and control all system events. figure 3. ADSP-BF534/adsp-bf536/adsp-bf537 memory maps reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sram (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram/cache (16k bytes) data bank b sram (16k bytes) data bank a sram/cache (16k bytes) async memory bank 3 (1m bytes) async memory bank 2 (1m bytes) async memory bank 1 (1m bytes) async memory bank 0 (1m bytes) sdram memory (16m bytes to 512m bytes) instruction sram/cache (16k bytes) i n te rn al m e m o ry m a p ex t e r na l m e mo r ym a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 data bank a sram (16k bytes) 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instruction bank a sram (32k bytes) reserved boot rom (2k bytes) 0xef00 0800 ADSP-BF534/adsp-bf537 memory map reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sram (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram/cache (16k bytes) data bank a sram/cache (16k bytes) async memory bank 3 (1m bytes) async memory bank 2 (1m bytes) async memory bank 1 (1m bytes) asyncmemorybank0(1mbytes) sdram memory (16m bytes to 512m bytes) instruction sram/cache (16k bytes) in te r n a l m e m o r y m a p e x te r n al me m o r y m ap 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instruction bank a sram (32k bytes) reserved reserved reserved boot rom (2k bytes) 0xef00 0800 adsp-bf536 memory map
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 7 of 68 | july 2010 conceptually, interrupts from the peripherals enter into the sic, and are then routed directly into the general-purpose inter- rupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leav ing seven prioritized interrupt inputs to support the peripheral s of the blackfin processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processor provides a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (iar). table 3 describes the inputs into the sic and the default mappings into the cec. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1reset rst 2 nonmaskable interrupt nmi 3exception evx 4reserved 5 hardware error ivhw 6 core timer ivtmr 7 general-purpose interrupt 7 ivg7 8 general-purpose interrupt 8 ivg8 9 general-purpose interrupt 9 ivg9 10 general-purpose interrupt 10 ivg10 11 general-purpose interrupt 11 ivg11 12 general-purpose interrupt 12 ivg12 13 general-purpose interrupt 13 ivg13 14 general-purpose interrupt 14 ivg14 15 general-purpose interrupt 15 ivg15 table 3. system interrupt controller (sic) peripheral interrupt event default mapping peripheral interrupt id pll wakeup ivg7 0 dma error (generic) ivg7 1 dmar0 block interrupt ivg7 1 dmar1 block interrupt ivg7 1 dmar0 overflow error ivg7 1 dmar1 overflow error ivg7 1 can error ivg7 2 ethernet error (adsp-bf536 and adsp-bf537 only) ivg7 2 sport 0 error ivg7 2 sport 1 error ivg7 2 ppi error ivg7 2 spi error ivg7 2 uart0 error ivg7 2 uart1 error ivg7 2 real-time clock ivg8 3 dma channel 0 (ppi) ivg8 4 dma channel 3 (sport 0 rx) ivg9 5 dma channel 4 (sport 0 tx) ivg9 6 dma channel 5 (sport 1 rx) ivg9 7 dma channel 6 (sport 1 tx) ivg9 8 twi ivg10 9 dma channel 7 (spi) ivg10 10 dma channel 8 (uart0 rx) ivg10 11 dma channel 9 (uart0 tx) ivg10 12 dma channel 10 (uart1 rx) ivg10 13 dma channel 11 (uart1 tx) ivg10 14 can rx ivg11 15 can tx ivg11 16 dma channel 1 (ethernet rx, adsp-bf536 and adsp-bf537 only) ivg11 17 port h interrupt a ivg11 17 dma channel 2 (ethernet tx, adsp-bf536 and adsp-bf537 only) ivg11 18 port h interrupt b ivg11 18 timer 0 ivg12 19 timer 1 ivg12 20 timer 2 ivg12 21 timer 3 ivg12 22 timer 4 ivg12 23 timer 5 ivg12 24 timer 6 ivg12 25 timer 7 ivg12 26 port f, g interrupt a ivg12 27 port g interrupt b ivg12 28
rev. i | page 8 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 event control the blackfin processor provides a very flexible mechanism to control the processing of events. in the cec, three registers are used to coordinate and control events. each register is 32 bits wide: ? cec interrupt latch register (ilat) C indicates when events have been latched. the appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. this register is updated automatically by the controller, but it can be writ- ten only when its corresponding imask bit is cleared. ? cec interrupt mask regist er (imask) C controls the masking and unmasking of indivi dual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when a sserted. a cleared bit in the imask register masks the event, preventing the processor from servicing the event even though the event may be latched in the ilat register. th is register can be read or written while in supervisor mode. (note that general-pur- pose interrupts can be globally enabled and disabled with the sti and cli instructions, respectively.) ? cec interrupt pending regi ster (ipend) C the ipend register keeps track of all nested events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but can be re ad while in supervisor mode. the sic allows further control of event processing by providing three 32-bit interrupt control and status registers. each register contains a bit corresponding to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask register (sic_imask) C controls the masking and unmasking of each peripheral interrupt event. when a bit is set in the regist er, that peripheral event is unmasked and is processed by the system when asserted. a cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. ? sic interrupt status regist er (sic_isr) C as multiple peripherals can be ma pped to a single event, this register allows the software to dete rmine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wake-up enable register (sic_iwr) C by enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. ( for more infor- mation, see dynamic power management on page 13. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recognizes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend output asserted is three core clock cycles; however, the latenc y can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the blackfin processors have multiple, independent dma channels that support automated data transfers with minimal overhead for the processor core. dma transfers can occur between the processors internal memories and any of its dma- capable peripherals. additionally, dma transfers can be accom- plished between any of the dma-capable peripherals and external devices connected to th e external memory interfaces, including the sdram controller and the asynchronous mem- ory controller. dma-capable peri pherals include the ethernet mac (adsp-bf536 and adsp-bf537 only), sports, spi port, uarts, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the dma controller supports both one-dimensional (1-d) and two-dimensional (2-d) dma tran sfers. dma transfer initial- ization can be implemented from registers or from sets of parameters called descriptor blocks. the 2-d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types suppo rted by the dma controller include ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address with in a common page. dma channels 12 and 13 (memory dma stream 0) ivg13 29 dma channels 14 and 15 (memory dma stream 1) ivg13 30 software watchdog timer ivg13 31 port f interrupt b ivg13 31 table 3. system interrupt controller (sic) (continued) peripheral interrupt event default mapping peripheral interrupt id
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 9 of 68 | july 2010 in addition to the dedicated peripheral dma channels, there are two memory dma channels provid ed for transfers between the various memories of the proce ssor system. this enables trans- fers of blocks of data betwee n any of the memoriesincluding external sdram, rom, sram, and flash memorywith mini- mal processor intervention. me mory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. the ADSP-BF534/adsp-bf536/ad sp-bf537 processors also have an external dma controller capability via dual external dma request pins when used in conjunction with the external bus interface unit (ebiu). this fu nctionality can be used when a high speed interface is required for external fifos and high bandwidth communications periph erals such as usb 2.0. it allows control of the number of data transfers for memdma. the number of transfers per edge is programmable. this feature can be programmed to allow memdma to have an increased priority on the external bus relative to the core. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 kh z crystal external to the processor. the rtc peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a lo w power state. the rtc provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on pro- grammable stopwatch countdown, or interrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day, while the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wake-up event. additionally, an rtc wake-up event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from the hibernate operating mode. connect rtc pins rtxi and rtxo with external components as shown in figure 4 . watchdog timer the ADSP-BF534/adsp-bf536/adsp-bf537 processors include a 32-bit timer that can be used to implement a software watchdog function. a software watchdog can improve system availability by forcing the proc essor to a known state through generation of a system reset, nonmaskable interrupt (nmi), or general-purpose interrupt, if the timer expires before being reset by software. the programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the progra mmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hard ware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the wa tchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk), at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the processor. eight timers have an external pin that can be con- figured either as a pulse-width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri ods of external events. these timers can be synchronized to an external clock input to the sev- eral other associated pf pins, to an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the two uarts and the can controller to measur e the width of the pulses in the data stream to provide a soft ware auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchronization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generating periodic in terrupts in an operating system. figure 4. external components for rtc rtxo c1 c2 x1 suggested components: x1 = ecliptek ec38j (through-hole package) or epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
rev. i | page 10 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 serial ports (sports) the ADSP-BF534/adsp-bf536/ adsp-bf537 processors incorporate two dual-channel synchronous serial ports (sport0 and sport1) for seri al and multiprocessor commu- nications. the sports support the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pi ns, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 bits to 32 bits in leng th, transferred mo st significant bit first or least significant bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts C each transmit a nd receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) port the ADSP-BF534/adsp-bf536/ad sp-bf537 processors have an spi-compatible port that en ables the processor to communi- cate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi de vices. the spi select pins are reconfigured programmable flag pins. using these pins, the spi port provides a full-duplex, sync hronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has an integrated dma controller, configurable to support transmit or receive data streams. the spis dma controller can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud regi ster contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports the ADSP-BF534/adsp-bf536/a dsp-bf537 processors pro- vide two full-duplex universal asynchronous receiver and transmitter (uart) ports, which are fully compatible with pc- standard uarts. each uart port provides a simplified uart interface to other peripherals or hosts, supporting full-duplex, dma-supported, asynchronous tr ansfers of serial data. a uart port includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. each uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. each uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 bits to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uartx_divisor comes from the uartx_dlh register (most significant 8 bits) and uartx_dll register (least significant 8 bits). spi clock rate f sclk 2 spi_baud ----------------------------------- - = uart clock rate f sclk 16 uartx_divisor -------------------------------------------------- =
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 11 of 68 | july 2010 in conjunction with the general-purpose timer functions, auto- baud detection is supported. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda ? ) serial infrared physical layer link specification (sir) protocol. controller area network (can) the ADSP-BF534/adsp-bf536/ad sp-bf537 processors offer a can controller that is a communication controller imple- menting the can 2.0b (active) protocol. this protocol is an asynchronous communications protocol used in both industrial and automotive control systems. the can protocol is well- suited for control applications du e to its capability to communi- cate reliably over a network, since the protocol incorporates crc checking message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (eight receive only, eight transmit only, 16 configurable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29-bit) identifier (id) message formats. ? support for remote frames. ? active or passive network support. ? can wake-up from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error, global. the electrical characteristics of each network connection are very demanding so the can interface is typically divided into two parts: a controller and a tran sceiver. this allows a single controller to support different drivers and can networks. the can module represents only the controller part of the interface. the controller interface supports connection to 3.3 v high- speed, fault-tolerant, single-wire transceivers. twi controller interface the ADSP-BF534/adsp-bf536/adsp-bf537 processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is compatible with the widely used i 2 c ? bus standard. the twi module offers the capabiliti es of simultaneous master and slave operation, support for both 7-bit addressing and multime- dia data arbitration. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at speeds up to 400 kbps. the twi interface pins are compatible with 5 v logic levels. additionally, the processors tw i module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. 10/100 ethernet mac the adsp-bf536 and adsp-bf537 processors offer the capa- bility to directly connect to a network by way of an embedded fast ethernet media access co ntroller (mac) that supports both 10-baset (10 mbps) and 100-baset (100 mbps) operation. the 10/100 ethernet mac peripheral is fully compliant to the ieee 802.3-2002 standard, and it provides programmable fea- tures designed to minimize supe rvision, bus use, or message processing by the rest of the processor system. some standard features are ? support of mii and rmii protocols for external phys. ? full duplex and half duplex modes. ? data framing and encapsulation: generation and detection of preamble, length padding, and fcs. ? media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision fr ames and of back-off timing. ? flow control (in full-duplex operation): generation and detection of pause frames. ? station management: generation of mdc/mdio frames for read-write access to phy registers. ? sclk operating range down to 25 mhz (active and sleep operating modes). ? internal loopback from tx to rx. some advanced features are ? buffered crystal output to external phy for support of a single crystal system. ? automatic checksum computation of ip header and ip payload fields of rx frames. ? independent 32-bit descriptor-driven rx and tx dma channels. ? frame status delivery to memory via dma, including frame completion semaphores , for efficient buffer queue management in software. ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations. ? convenient frame alignment modes support even 32-bit alignment of encapsulated rx or tx ip packet data in mem- ory after the 14-byte mac header. ? programmable ethernet event interrupt supports any com- bination of ? any selected rx or tx frame status conditions. ? phy interrupt condition. ? wake-up frame detected. ? any selected mac management counter(s) at half-full. ? dma descriptor error. ? 47 mac management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value.
rev. i | page 12 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 ? programmable rx address fi lters, including a 64-bit address hash table for multicast and/or unicast frames, and programmable filter modes fo r broadcast, multicast, uni- cast, control, and damaged frames. ? advanced power management supporting unattended transfer of rx and tx frames and status to/from external memory via dma during low power sleep mode. ? system wake-up from sleep operating mode upon magic packet or any of four user-definable wake-up frame filters. ? support for 802.3q tagged vlan frames. ?programmable mdc clock rate and preamble suppression. ? in rmii operation, 7 unused pins can be configured as gpio pins for other purposes. ports the ADSP-BF534/adsp-bf536/ adsp-bf537 processors group the many peripheral signals to four portsport f, port g, port h, and port j. most of th e associated pins are shared by multiple signals. the ports function as multiplexer controls. eight of the pins (port f7C0) offer high source/high sink current capabilities. general-purpose i/o (gpio) the processors have 48 bidirectional, general-purpose i/o (gpio) pins allocated across three separate gpio modules portfio, portgio, and porthio, associated with port f, port g, and port h, respectively. port j does not provide gpio functionality. each gpio-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output or input drivers are active by default. each general-purpose port pin can be individually con- trolled by manipulation of the po rt control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status registers C the processors employ a write one to modify mechanism that allows any combi- nation of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. four control registers ar e provided. one register is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. reading the gpio status register allows software to interrogate the sense of the pins. ? gpio interrupt mask register s C the two gpio interrupt mask registers allow each indi vidual gpio pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual pin values, one gpio interrupt mask register sets bits to enable interrupt function, and the other gpio interrupt mask register clears bits to disable interrupt function. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C the two gpio inter- rupt sensitivity registers specif y whether individual pins are level- or edge-sensitive and specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. parallel peripheral interface (ppi) the processor provides a parallel peripheral interface (ppi) that can connect directly to parallel adc and dac converters, video encoders and decoders, and othe r general-purpose peripherals. the ppi consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate and the synchronization signals can be configured as either inputs or outputs. the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general-purpose mode, the ppi provides half-duplex, bidirectional data transfer with up to 16 bits of data. up to three frame synchr onization signals are also pro- vided. in itu-r 656 mode, th e ppi provides half-duplex bidirectional transfer of 8- or 10-bit video data. additionally, on-chip decode of embedded start-of-line (sol) and start-of- field (sof) preamble packets is supported. general-purpose mo de descriptions the general-purpose modes of the ppi are intended to suit a wide variety of data capture and transmission applications. three distinct subm odes are supported: 1. input mode C frame syncs and data are inputs into the ppi. 2. frame capture mode C frame syncs are outputs from the ppi, but data are inputs. 3. output mode C frame syncs and data are outputs from the ppi. input mode input mode is intended for adc applications, as well as video communication with hardware sign aling. in its simplest form, ppi_fs1 is an external frame sync input that controls when to read data. the ppi_delay mmr allows for a delay (in ppi_clk cycles) between receptio n of this frame sync and the initiation of data reads. the number of input data samples is user programmable and defined by the contents of the ppi_count register. the ppi supports 8-bit and 10-bit through 16-bit data, programm able in the ppi_control register.
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 13 of 68 | july 2010 frame capture mode frame capture mode allows the video source(s) to act as a slave (for frame capture for example). the ADSP-BF534/ adsp-bf536/adsp-bf537 processo rs control when to read from the video source(s). ppi_fs1 is an hsync output and ppi_fs2 is a vsync output. output mode output mode is used for transmitting video or other data with up to three output frame syncs. typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. itu-r 656 mode descriptions the itu-r 656 modes of the ppi ar e intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct submodes are supported: 1. active video only mode 2. vertical blanking only mode 3. entire field mode active video mode active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. the ppi does not read in any da ta between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vert ical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. afte r synchronizing to the start of field 1, the ppi ignores incoming samples until it sees an sav code. the user specifies the number of active video lines per frame (in ppi_count register). vertical blanking interval mode in this mode, the ppi only transf ers vertical blanking interval (vbi) data. entire field mode in this mode, the entire incoming bit stream is read in through the ppi. this includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and ver- tical blanking intervals. data transfer starts immediately after synchronization to field 1. data is transferred to or from the synchronous channels through eight dma engines that work autonomously from the processor core. dynamic power management the ADSP-BF534/adsp-bf536/adsp-bf537 processors pro- vide five operating modes, each with a different performance and power profile. in addition, dynamic power management provides the control functions to dynamically alter the proces- sor core supply voltage, furt her reducing power dissipation. control of clocking to each of the peripherals also reduces power consumption. see table 4 for a summary of the power settings for each mode. also, see table 16 , table 15 and table 17 . full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not real ized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. in the active mode, it is possibl e to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally an external event or rtc ac tivity wakes up the processor. when in the sleep mode, assertin g wake-up causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled , the processor transitions to the full on mode. if bypass is enabled, the processor transi- tions to the active mode. system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proc essor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchro nous interrupt causes the table 4. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) internal power (v ddint ) full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. i | page 14 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 processor to transition to the active mode. assertion of reset while in deep sleep mode causes the processor to transition to the full-on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and to all of the synchronous peripherals (sclk). the internal voltage regu- lator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl regi ster. this disables both cclk and sclk. furthermore, it sets the internal power supply volt- age (v ddint ) to 0 v to provide the greatest power savings. to preserve the processor state, prio r to removing power, any criti- cal information stored interna lly (memory contents, register contents, etc.) must be written to a nonvolatile storage device. since v ddext is still supplied in this st ate, all of the external pins three-state, unless otherwise specif ied. this allows other devices that are connected to the processor to still have power applied without drawing unwanted current. the ethernet or can modules can wake up the internal supply regulator. if the ph6 pin does not connect as the phyint sig- nal to an external phy device, it can be pulled low by any other device to wake the processor up. the regulator can also be woken up by a real-time clock wake-up event or by asserting the reset pin. all hibernate wake-up events initiate the hardware reset sequence. individual sour ces are enabled by the vr_ctl register. with the exception of the vr_c tl and the rtc registers, all internal registers and memories lose their content in the hiber- nate state. state variables can be held in external sram or sdram. the sckelow bit in the vr_ctl register provides a means of waking from hibernate state without disrupting a self- refreshing sdram, provided that there is also an external pull- down on the scke pin. power savings as shown in table 5 , the processors support three different power domains which maximizes flexibility, while maintaining compliance with industry standa rds and conventions. by isolat- ing the internal logic of the processor into its own power domain, separate from the rtc and other i/o, the processor can take advantage of dynamic power management, without affecting the rtc or other i/o de vices. there are no sequencing requirements for the various power domains. the dynamic power management feature allows both the pro- cessors input voltage (v ddint ) and clock frequency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in power dissipation, while reducing the voltage by 25% reduces power di ssipation by more than 40%. further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. the power savings factor (psf) is calculated as: where: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage t nom is the duration running at f cclknom t red is the duration running at f cclkred the percent power savings is calculated as voltage regulation the ADSP-BF534/adsp-bf536/a dsp-bf537 processors pro- vide an on-chip voltage regulato r that can generate appropriate v ddint voltage levels from the v ddext supply. see operating conditions on page 24 for regulator tolerances and acceptable v ddext ranges for specific models. table 5. power domains power domain v dd range all internal logic, except rtc v ddint rtc internal logic and crystal i/o v ddrtc all other i/o v ddext figure 5. voltage regulator circuit psf f cclkred f cclknom --------------------- v ddintred v ddintnom -------------------------- ?? ?? 2 t red t nom ---------- - ? ? ? ? = % power savings 1 psf ? () 100 % = v ddext (low-inductance) v ddint vr out 100f vr out gnd short and low- inductance wire v ddext + + + 100f 100f 10f low esr 100nf set of decoupling capacitors fds9431a zhcs1000 note: designer should minimize trace length to fds9431a. 10h
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 15 of 68 | july 2010 figure 5 shows the typical external components required to complete the power management system. the regulator con- trols the internal logic voltage le vels and is programmable with the voltage regulator control regi ster (vr_ctl) in increments of 50 mv. to reduce standby po wer consumption, the internal voltage regulator can be progra mmed to remove power to the processor core while keeping i/o power supplied. while in hibernate state, v ddext can still be applied, eliminating the need for external buffers. the voltage regulator can be activated from this power-down state by asserting the reset pin, which then initiates a boot sequence. the regu lator can also be disabled and bypassed at the users discretion . for additional information on voltage regulation, see switching regulator design consider- ations for the adsp-bf533 blackfin processors (ee-228) . clock signals the ADSP-BF534/adsp-bf536/ad sp-bf537 processors can be clocked by an external crysta l, a sine wave input, or a buff- ered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the processors include an on-chip oscilla- tor circuit, an external crysta l can be used. for fundamental frequency operation, us e the circuit shown in figure 6 . a parallel-resonant, fundamenta l frequency, microprocessor- grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k range. further parallel resistors are typically not rec- ommended. the two capa citors and the series resistor shown in figure 6 fine-tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 6 are typical values only. the capaci tor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations of multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in the application note using third overtone crystals with the adsp-218x dsp (ee-168) . the clkbuf pin is an output pin, and is a buffer version of the input clock. this pin is particularly useful in ethernet applica- tions to limit the number of required clock sources in the system. in this type of application, a single 25 mhz or 50 mhz crystal can be applied directly to the processors. the 25 mhz or 50 mhz output of clkbuf can then be connected to an exter- nal ethernet mii or rmii phy device. because of the default 10 pll multiplier, providing a 50 mhz clkin exceeds the recommended operating conditions of the lower speed grades. because of this restriction, an rmii phy requiring a 50 mhz clock input cann ot be clocked directly from the clkbuf pin for the lower speed grades. in this case, either provide a separate 50 mhz clock source, or use an rmii phy with 25 mhz clock input options. the clkbuf output is active by default and can be disabled using the vr_ctl register for power savings. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 7 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programmab le 0.5 to 64 multiplication factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 10, but it can be modi- fied by a software instruction se quence in the pll_ctl register. on-the-fly cclk and sclk frequency changes can be effected by simply writing to the pll_div register. whereas the maxi- mum allowed cclk and sclk rates depend on the applied voltages v ddint and v ddext , the vco is always permitted to run up to the frequency specified by the parts speed grade. the clkout pin reflects the sclk frequency to the off-chip world. it belongs to the sdram interface, but it functions as a refer- figure 6. external crystal connections figure 7. frequency mo dification methods clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customied depending on the crystal and layout. please analye carefully. 18 pf * en 18 pf * 330
rev. i | page 16 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 ence signal in other timing specifications as well. while active by default, it can be disabled using the ebiu_sdgctl and ebiu_amgctl registers. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. the maximum cclk frequency not only depends on the parts speed grade (see ordering guide on page 68 ), it also depends on the applied v ddint voltage (see table 10 , table 11 , and table 12 on page 25 for details). the maximal system clock rate (sclk) depends on the chip package and the applied v ddext voltage (see table 14 on page 25 ). booting modes the ADSP-BF534/adsp-bf536/a dsp-bf537 processor has six mechanisms (listed in table 8 ) for automatically loading inter- nal and external memory after a reset. a seventh mode is provided to execute from extern al memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory C execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). ? boot from 8-bit and 16-bit external flash memory C the 8-bit or 16-bit flash boot routine located in boot rom memory space is set up using asynchronous memory bank 0. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). the boot rom evaluates the first byte of the boot st ream at address 0x2000 0000. if it is 0x40, 8-bit boot is performed. a 0x60 byte assumes a 16-bit memory device and performs 8-bit dma. a 0x20 byte also assumes 16-bit memory but performs 16-bit dma. ? boot from serial spi memory (eeprom or flash) C 8-, 16-, or 24-bit addressable devices are supported as well as at45db041, at45db081, at45db161, at45db321, at45db642, and at45db1282 dataflash ? devices from atmel. the spi uses the pf10/spi ssel1 output pin to select a single spi eeprom/flash device, submits a read command and successive addre ss bytes (0x00) until a valid 8-, 16-, or 24-bit, or atmel ad dressable device is detected, and begins clocking data into the processor. ? boot from spi host device C the blackfin processor oper- ates in spi slave mode and is configured to receive the bytes of the .ldr file from an spi host (master) agent. to hold off the host device from transmitting while the boot rom is busy, the blackfin processo r asserts a gpio pin, called host wait (hwait), to signal the host device not to send any more bytes until the flag is deasserted. the flag is cho- sen by the user and this information is transferred to the blackfin processor via bits 10:5 of the flag header. ? boot from uart C using an autobaud handshake sequence, a boot-stream-formatted program is downloaded by the host. the host agent selects a baud rate within the uarts clocking capabilities. when performing the auto- baud, the uart expects an @ (boot stream) character table 6. example system clock ratios signal name ssel3C0 divider ratio vco:sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 7. core clock ratios signal name csel1C0 divider ratio vco:cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 table 8. booting modes bmode2C0 description 000 execute from 16-bit external memory (bypass boot rom) 001 boot from 8-bit or 16-bit memory (eprom/flash) 010 reserved 011 boot from serial spi memory (eeprom/flash) 100 boot from spi host (slave mode) 101 boot from serial twi memory (eeprom/flash) 110 boot from twi host (slave mode) 111 boot from uart host (slave mode)
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 17 of 68 | july 2010 (8 bits data, 1 start bit, 1 stop bit, no parity bit) on the rxd pin to determine the bit rate. it then replies with an acknowledgement that is comp osed of 4 bytes: 0xbf, the value of uart_dll, the value of uart_dlh, and 0x00. the host can then download the boot stream. when the processor needs to hold off the host, it deasserts cts. therefore, the host must monitor this signal. ? boot from serial twi memo ry (eeprom/flash) C the blackfin processor operates in master mode and selects the twi slave with the un ique id 0xa0. it submits successive read commands to the memory device starting at 2-byte internal address 0x0000 and begi ns clocking data into the processor. the twi memory de vice should comply with philips i 2 c bus specification version 2.1 and have the capa- bility to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. ? boot from twi host C the twi host agent selects the slave with the unique id 0x5f. th e processor replies with an acknowledgement and the host can then download the boot stream. the twi host agent should comply with philips i 2 c bus specification version 2.1. an i 2 c multi- plexer can be used to select one processor at a time when booting multiple processors from a single twi. for each of the boot modes, a 10- byte header is first brought in from an external device. the he ader specifies the number of bytes to be transferred and th e memory destination address. multiple memory blocks can be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, th e processor jumps directly to the beginning of l1 instruction memory. to augment the boot modes, a se condary software loader can be added to provide additional bo oting mechanisms. this second- ary loader could provide the capability to boot from flash, variable baud rate, and other sour ces. in all boot modes except bypass, program execution star ts from on-chip l1 memory address 0xffa0 0000. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which ta kes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mc u features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store mo dified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16-bit and 32-bit instru ctions (no mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools blackfin processors are suppor ted with a complete set of crosscore ? ? software and hardware development tools, including analog devices emulators and the visualdsp++ ? ? development environment. the sa me emulator hardware that supports other analog devices processors also fully emulates the blackfin processor family. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assemble r that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-leve l simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathemati- cal functions. a key point fo r these tools is c/c++ code efficiency. the compiler has been developed for efficient translation of c/c++ code to blackfin assembly. the blackfin processor has architectural featur es that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the so ftware developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and ? crosscore is a registered trad emark of analog devices, inc. ? visualdsp++ is a registered trademark of analog devices, inc.
rev. i | page 18 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 efficiently. by using the profil er, the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can ? view mixed c/c++ and assembly code (interleaved source and object information). ? insert breakpoints. ? set conditional breakpoints on registers, memory, and stacks. ? trace instruction execution. ? perform linear or statistical profiling of program execution. ? fill, dump, and graphically pl ot the contents of memory. ? perform source level debugging. ? create custom debugger windows. the visualdsp++ ide lets programmers define and manage software development. its dialog boxes and prop erty pages let programmers configure and mana ge all development tools, including color syntax highlighting in the visualdsp++ editor. these capabilities pe rmit programmers to ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one correspondence with the tools command line switches. the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of embedded, real-time programming. these ca pabilities enable engineers to develop code more effectively, eliminat ing the need to start from the very beginning when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vdk also supports priority-based, pre-emptive, coop erative, and time-sliced sched- uling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used with standard command line tools. when the vdk is used, the development environment assists the develope r with many error prone tasks and assists in managing system resources, automating the gen- eration of various vdk-based objects, and visualizing the system state when debugging an application that uses the vdk. the expert linker can be used to visually manipulate the place- ment of code and data in the embedded system. memory utilization can be viewed in a color-coded graphical form. code and data can be easily moved to different areas of the processor or external memory with the dr ag of the mouse. runtime stack and heap usage can be examined. the expert linker is fully com- patible with existing linker definition file (ldf), allowing the developer to move between the graphical and textual environments. analog devices emulators use the ieee 1149.1 jtag test access port of the blackfin to monito r and control the target board processor during emulation. th e emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emula- tion is assured by the use of th e processors jtag interfacethe emulator does not affect targ et system load ing or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the bl ackfin processor family. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. ez-kit lite? evaluation board for evaluation of adsp-b f534/adsp-bf536/adsp-bf537 processors, use the adsp-bf537 ez-kit lite board available from analog devices. order part number adds-bf537-ezlite. the bo ard comes with on-chip emulation capabilities and is equipped to enable software development. multiple daug hter cards are available. designing an emulator-compatible processor board the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog de vices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag processor. the emulator uses the tap to access th e internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memo ry, and examine registers. the processor must be halted to se nd data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see analog devices jtag emul ation technical reference (ee-68) on the analog devices website under www.analog.com/ee-notes . this document is updated regularly to keep pace with improvements to emulator support.
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 19 of 68 | july 2010 related documents the following publications th at describe the ADSP-BF534/ adsp-bf536/adsp-bf537 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf537 blackfin proc essor hardware reference ? adsp-bf53x/adsp-bf56x blackfin processor program- ming reference ? ADSP-BF534/adsp-bf536/adsp-bf537 blackfin proces- sor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains page in the circuits from the lab tm site ( http://www.analog. com/signalchains ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
rev. i | page 20 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 pin descriptions the ADSP-BF534/adsp-bf536/ad sp-bf537 processors pin definitions are listed in table 9 . in order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functions. in cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. pins shown with an aster- isk after their name (*) offer high source/high sink current capabilities. all pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchro- nous and synchronous memory control, and the buffered xtal output pin (clkbuf). on the external memory interface, the control and address lines are driv en high, with the exception of clkout, which toggles at the system clock rate. if br is active (whether or not reset is asserted), the me mory pins are also three-stated. during hibernate, all outputs are three-stated unless otherwise noted in table 9 . all i/o pins have their input buffe rs disabled with the exception of the pins noted in the data sheet that need pull-ups or pull- downs if unused. the sda (serial data) and scl (ser ial clock) pins are open drain and therefore require a pull-up resistor. consult version 2.1 of the i 2 c specification for the proper resistor value. table 9. pin descriptions pin name type function driver type 1 memory interface addr19C1 o address bus for async access a data15C0 i/o data bus for async/sync access a abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a br i bus request (this pin should be pulled high when not used.) bg obus grant a bgh o bus grant hang a asynchronous memory control ams3C0 o bank select (require pull-ups if hibernate is used.) a ardy i hardware ready control aoe o output enable a are oread enable a awe owrite enable a synchronous memory control sras o row address strobe a scas o column address strobe a swe owrite enable a scke o clock enable(requires a pull-down if hibernate with sdram self-refresh is used.) a clkout o clock output b sa10 o a10 pin a sms obank select a
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 21 of 68 | july 2010 port f: gpio/uart1C0/timer7C0/spi/ external dma request/ppi (* = high source/high sink pin) pf0* C gpio/ uart0 tx / dmar0 i/o gpio/ uart0 transmit / dma request 0 c pf1* C gpio/ uart0 rx / dmar1 / taci1 i/o gpio/ uart0 receive / dma request 1 / timer1 alternate input capture c pf2* C gpio/ uart1 tx / tmr7 i/o gpio/ uart1 transmit / timer7 c pf3* C gpio/ uart1 rx / tmr6 / taci6 i/o gpio/ uart1 receive / timer6 / timer6 alternate input capture c pf4* C gpio/ tmr5 / spi ssel6 i/o gpio/ timer5 / spi slave select enable 6 c pf5* C gpio/ tmr4 / spi ssel5 i/o gpio/ timer4 / spi slave select enable 5 c pf6* C gpio/ tmr3 / spi ssel4 i/o gpio/ timer3 / spi slave select enable 4 c pf7* C gpio/ tmr2 / ppi fs3 i/o gpio/ timer2 / ppi frame sync 3 c pf8 C gpio/ tmr1 / ppi fs2 i/o gpio/ timer1 / ppi frame sync 2 c pf9 C gpio/ tmr0 / ppi fs1 i/o gpio/ timer0 / ppi frame sync 1 c pf10 C gpio/ sp i sse l1 i/o gpio/ spi slave select enable 1 c pf11 C gpio/ spi mosi i/o gpio/ spi master out slave in c pf12 C gpio/ spi miso i/o gpio/ spi master in slave out (this pin should be pulled high through a 4.7 k resistor if booting via the spi port.) c pf13 C gpio/ spi sck i/o gpio/ spi clock d pf14 C gpio/ spi ss / taclk0 i/o gpio/ spi slave select / alternate timer0 clock input c pf15 C gpio/ ppi clk / tmrclk i/o gpio/ ppi clock / external timer reference c port g: gpio/ppi/sport1 pg0 C gpio/ ppi d0 i/o gpio/ ppi data 0 c pg1 C gpio/ ppi d1 i/o gpio/ ppi data 1 c pg2 C gpio/ ppi d2 i/o gpio/ ppi data 2 c pg3 C gpio/ ppi d3 i/o gpio/ ppi data 3 c pg4 C gpio/ ppi d4 i/o gpio/ ppi data 4 c pg5 C gpio/ ppi d5 i/o gpio/ ppi data 5 c pg6 C gpio/ ppi d6 i/o gpio/ ppi data 6 c pg7 C gpio/ ppi d7 i/o gpio/ ppi data 7 c pg8 C gpio/ ppi d8 / dr1sec i/o gpio/ ppi data 8 / sport1 receive data secondary c pg9 C gpio/ ppi d9 / dt1sec i/o gpio/ ppi data 9 / sport1 transmit data secondary c pg10 C gpio/ pp i d 1 0 / rsclk1 i/o gpio/ ppi data 10 / sport1 receive serial clock d pg11 C gpio/ ppi d11 / rfs1 i/o gpio/ ppi data 11 / sport1 receive frame sync c pg12 C gpio/ ppi d12 / dr1pri i/o gpio/ ppi data 12 / sport1 receive data primary c pg13 C gpio/ ppi d13 / tsclk1 i/o gpio/ ppi data 13 / sport1 transmit serial clock d pg14 C gpio/ ppi d14 / tfs1 i/o gpio/ ppi data 14 / sport1 transmit frame sync c pg15 C gpio/ ppi d15 / dt1pri i/o gpio/ ppi data 15 / sport1 transmit data primary c table 9. pin descriptions (continued) pin name type function driver type 1
rev. i | page 22 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 port h: gpio/10/100 ethernet mac (on ADSP-BF534, these pins are gpio only) ph0 C gpio/ etxd0 i/o gpio/ ethernet mii or rmii transmit d0 e ph1 C gpio/ etxd1 i/o gpio/ ethernet mii or rmii transmit d1 e ph2 C gpio/ etxd2 i/o gpio/ ethernet mii transmit d2 e ph3 C gpio/ etxd3 i/o gpio/ ethernet mii transmit d3 e ph4 C gpio/ etxen i/o gpio/ ethernet mii or rmii transmit enable e ph5 C gpio/ mii txclk / rmii ref_clk i/o gpio/ ethernet mii transmit clock / rmii reference clock e ph6 C gpio/ mii phyint / rmii mdint i/o gpio/ ethernet mii phy interrupt / rmii management data interrupt (this pin should be pulled high when used as a hibernate wake-up.) e ph7 C gpio/ col i/o gpio/ ethernet collision e ph8 C gpio/ erxd0 i/o gpio/ ethernet mii or rmii receive d0 e ph9 C gpio/ erxd1 i/o gpio/ ethernet mii or rmii receive d1 e ph10 C gpio/ erxd2 i/o gpio/ ethernet mii receive d2 e ph11 C gpio/ erxd3 i/o gpio/ ethernet mii receive d3 e ph12 C gpio/ erxdv / taclk5 i/o gpio/ ethernet mii receive data valid / alternate timer5 input clock e ph13 C gpio/ erxclk / taclk6 i/o gpio/ ethernet mii receive clock / alternate timer6 input clock e ph14 C gpio/ erxer / taclk7 i/o gpio/ ethernet mii or rmii receive error / alternate timer7 input clock e ph15 C gpio/ mii crs / rmii crs_dv i/o gpio/ ethernet mii carrier sense / ethernet rmii carrier sense and receive data valid e port j: sport0/twi/spi select/can pj0 C mdc o ethernet management channel clock (on ADSP-BF534 processors, do not connect this pin.) e pj1 C mdio i/o ethernet management channel serial data (on ADSP-BF534 processors, tie this pin to ground.) e pj2 C scl i/o twi serial clock (this pin is an open-drain output and requires a pull-up resistor.) f pj3 C sda i/o twi serial data (this pin is an open-drain output and requires a pull-up resistor.) f pj4 C dr0sec/ canrx / taci0 i sport0 receive data secondary/ can receive / timer0 alternate input capture pj5 C dt0sec/ cantx / spi ssel7 o sport0 transmit data secondary/ can transmit / spi slave select enable 7 c pj6 C rsclk0/ taclk2 i/o sport0 receive serial clock/ alternate timer2 clock input d pj7 C rfs0/ taclk3 i/o sport0 receive frame sync/ alternate timer3 clock input c pj8 C dr0pri/ taclk4 i sport0 receive data primary/ alternate timer4 clock input pj9 C tsclk0/ taclk1 i/o sport0 transmit serial clock/ alternate timer1 clock input d pj10 C tfs0/ spi ssel3 i/o sport0 transmit frame sync/ spi slave select enable 3 c pj11 C dt0pri/ spi ssel2 o sport0 transmit data primary/ spi slave select enable 2 c real-time clock rtxi i rtc crystal input (this pin should be pulled low when not used.) rtxo o rtc crystal output (does not three-state in hibernate.) jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this pin should be pulled low if the jtag port is not used.) emu o emulation output c table 9. pin descriptions (continued) pin name type function driver type 1
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 23 of 68 | july 2010 clock clkin i clock/crystal input xtal o crystal output (if clkbuf is enabled, does not three-state during hibernate.) clkbuf o buffered xtal output (if enabled, does not three-state during hibernate.) e mode controls reset ireset nmi i nonmaskable interrupt (this pin shou ld be pulled high when not used.) bmode2C0 i boot mode strap 2-0 (these pins must be pulled to the state required for the desired boot mode.) voltage regulator vrout1C0 o external fet drive (these pins sh ould be left unconnected when not used and are driven high during hibernate.) supplies v ddext p i/o power supply v ddint p internal power supply v ddrtc p real-time clock power supply (this pin should be connected to v ddext when not used and should remain powered at all times.) gnd g external ground 1 see output drive currents on page 51 for more information about each driver types. table 9. pin descriptions (continued) pin name type function driver type 1
rev. i | page 24 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 specifications note that component specificat ions are subject to change without notice. operating conditions parameter conditions min nominal max unit v ddint internal supply voltage 1 1 the regulator can generate v ddint at levels of 0.85 v to 1.2 v with C5% to +10% tolerance, 1.25 v with C4% to +10% to lerance, and 1.3 v with C0% to +10% toleran ce. the required v ddint is a function of speed grade and operating frequency. see table 10 , table 11 , and table 12 for details. nonautomotive 300 mhz, 400 mhz, and 500 mhz speed grade models 2 2 see ordering guide on page 68 . 0.8 1.2 1.32 v v ddint internal supply voltage 1 nonautomotive 533 mhz speed grade models 2 0.8 1.25 1.375 v v ddint internal supply voltage 1 nonautomotive 600 mhz speed grade models 2 0.8 1.3 1.43 v v ddint internal supply voltage 1 automotive grade models and +105c nonautomotive grade models 2 0.95 1.2 1.32 v v ddext external supply voltage nonautomotive grade models 2 2.25 2.5 or 3.3 3.6 v v ddext external supply voltage automotive grade models and +105c nonautomotive grade models 2 2.7 3.0 or 3.3 3.6 v v ddrtc real-time clock power supply voltage 2.25 3.6 v v ih high level input voltage 3, 4 3 bidirectional pins (data15C0, pf15C0, pg15C0, ph15C0, tfs0, tsclk0, rsclk0, rfs0, mdio) and input pins (br , ardy, dr0pri, dr0sec, rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode2C0) of the adsp -bf534/adsp-bf536/adsp-bf537 ar e 3.3 v-tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 4 parameter value applies to all input and bidi rectional pins except clkin, sda, and scl. v ddext = maximum 2.0 v v ihclkin high level input voltage 5 5 parameter value applies to clkin pin only. v ddext = maximum 2.2 v v ih5v 5.0 v tolerant pins, high level input voltage 6 6 applies to pins pj2/scl and pj3/sda which are 5.0 v tolerant (always accept up to 5.5 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 0.7 v ddext v v ih5v 5.0 v tolerant pins, high level input voltage 7 7 applies to pin pj4/dr0sec/canrx/tac i0 which is 5.0 v tolerant (alwa ys accepts up to 5.5 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. v ddext = maximum 2.0 v v il low level input voltage 3, 8 8 parameter value applies to all input an d bidirectional pins except sda and scl. v ddext = minimum +0.6 v v il5v 5.0 v tolerant pins, low level input voltage 6 0.3 v ddext v v il5v 5.0 v tolerant pins, low level input voltage 7 v ddext = minimum +0.8 v t j junction temperature 208-ball chip scale package ball grid array (csp_bga) @ t ambient = C40c to +105c C40 +120 c t j junction temperature 208-ball chip scale package ball grid array (csp_bga) @ t ambient = C40c to +85c C40 +105 c t j junction temperature 208-ball chip scale package ball grid array (csp_bga) @ t ambient = 0c to +70c 0+95c t j junction temperature 182-ball chip scale package ball grid array (csp_bga) @ t ambient = C40c to +85c C40 +105 c t j junction temperature 182-ball chip scale package ball grid array (csp_bga) @ t ambient = 0c to +70c 0+ 1 0 0 c
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 25 of 68 | july 2010 table 10 through table 12 describe the voltage/frequency requirements for the ADSP-BF534/adsp-bf536/adsp-bf537 processor clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed th e maximum core clock and system clock. table 13 describes phase-lock ed loop operating conditions. table 10. core clock requirements500 mh z, 533 mhz, and 600 mhz speed grades 1 parameter internal regulator setting max unit f cclk core clock frequency (v ddint =1.30 v minimum) 2 1.30 v 600 mhz f cclk core clock frequency (v ddint = 1.20 v minimum) 3 1.25 v 533 mhz f cclk core clock frequency (v ddint =1.14 v minimum) 1.20 v 500 mhz f cclk core clock frequency (v ddint =1.045 v minimum) 1.10 v 444 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 1.00 v 400 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 0.90 v 333 mhz f cclk core clock frequency (v ddint = 0.8 v minimum) 0.85 v 250 mhz 1 see ordering guide on page 68 . 2 applies to 600 mhz models only. see ordering guide on page 68 . 3 applies to 533 mhz and 60 0 mhz models only. see ordering guide on page 68 . table 11. core clock requirements400 mhz speed grade 1 120c t j > 105c all 2 other t j unit parameter internal regulator setting max max f cclk core clock frequency (v ddint =1.14 v minimum) 1.20 v 400 400 mhz f cclk core clock frequency (v ddint =1.045 v minimum) 1.10 v 333 363 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 1.00 v 295 333 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 0.90 v 280 mhz f cclk core clock frequency (v ddint = 0.8 v minimum) 0.85 v 250 mhz 1 see ordering guide on page 68 . 2 see operating conditions on page 24 . table 12. core clock requirements300 mhz speed grade 1 parameter internal regulator setting max unit f cclk core clock frequency (v ddint =1.14 v minimum) 1.20 v 300 mhz f cclk core clock frequency (v ddint =1.045 v minimum) 1.10 v 255 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 1.00 v 210 mhz f cclk core clock frequency (v ddint = 0.85 v minimum) 0.90 v 180 mhz f cclk core clock frequency (v ddint = 0.8 v minimum) 0.85 v 160 mhz 1 see ordering guide on page 68 . table 13. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 max f cclk mhz table 14. system clock requirements parameter condition max unit f sclk 1 v ddext = 3.3 v or 2.5 v, v ddint 1.14 v 133 2 mhz f sclk 1 v ddext = 3.3 v or 2.5 v, v ddint < 1.14 v 100 mhz 1 f sclk must be less than or equal to f cclk and is subject to additional restrict ions for sdram interface operation. see table 27 on page 35 . 2 rounded number. actual test specificat ion is sclk period of 7.5 ns. see table 27 on page 35 .
rev. i | page 26 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 electrical characteristics 300 mhz/400 mhz 1 500 mhz/533 mhz/600 mhz 2 parameter test conditions min typ max min typ max unit v oh 3 high level output voltage v ddext = 2.5 v/3.0 v/ 3.3 v 10%, i oh = C0.5 ma v ddext C 0.5 v ddext C 0.5 v v oh 4 v ddext = 3.3 v 10%, i oh = C8 ma v ddext = 2.5 v/3.0 v 10%, i oh = C6 ma v ddext C 0.5 v ddext C 0.5 v ddext C 0.5 v ddext C 0.5 v v v oh 5 v ddext = 2.5 v/3.0 v/ 3.3 v 10%, i oh = C2.0 ma v ddext C 0.5 v ddext C 0.5 v i oh 6 high level output current v oh = v ddext C 0.5 v min C64 C64 ma i oh 7 v oh = v ddext C 0.5 v min C144 C144 ma v ol 3 low level output voltage v ddext = 2.5 v/3.0 v/ 3.3 v 10%, i ol = 2.0 ma 0.4 0.4 v v ol 4 v ddext = 3.3 v 10%, i ol = 8 ma v ddext = 2.5 v/3.0 v 10%, i ol = 6 ma 0.5 0.5 0.5 0.5 v v v ol 5 v ddext = 2.5 v/3.0 v/ 3.3 v 10%, i ol = 2.0 ma 0.5 0.5 v i ol 6 low level output current v ol = 0.5 v max 64 64 ma i ol 7 v ol = 0.5 v max 144 144 ma i ih high level input current 8 v ddext =3.6 v, v in = 3.6 v 10 10 a i ih5v high level input current 9 v ddext =3.6 v, v in = 5.5 v 10 10 a i il low level input current 2 v ddext =3.6 v, v in = 0 v 10 10 a i ihp high level input current jtag 10 v ddext = 3.6 v, v in = 3.6 v 50 50 a i ozh three-state leakage current 11 v ddext = 3.6 v, v in = 3.6 v 10 10 a i ozh5v three-state leakage current 12 v ddext =3.6 v, v in = 5.5 v 10 10 a i ozl three-state leakage current 5 v ddext = 3.6 v, v in = 0 v 10 10 a
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 27 of 68 | july 2010 c in input capacitance 13, 14 f in = 1 mhz, t ambient = 25c, v in = 2.5 v 88 p f i dd-idle v ddint current in idle v ddint = 1.0 v, f cclk = 50 mhz, t j = 25c, asf = 0.43 14 24 ma i dd-typ v ddint current v ddint = 1.14 v, f cclk =300mhz, t j = 25c, asf = 1.00 100 113 ma i dd-typ v ddint current v ddint = 1.14 v, f cclk =400mhz, t j = 25c, asf = 1.00 125 138 ma i dddeepsleep 15 v ddint current in deep sleep mode v ddint = 1.0 v, f cclk = 0 mhz, t j = 25c, asf = 0.00 616ma i ddsleep v ddint current in sleep mode v ddint = 1.0 v, f sclk = 25 mhz, t j = 25c 9.5 19.5 ma i dd-typ v ddint current v ddint = 1.20 v, f cclk =533mhz, t j = 25c, asf = 1.00 185 ma i dd-typ v ddint current v ddint = 1.30 v, f cclk =600mhz, t j = 25c, asf = 1.00 227 ma i ddhibernate 15, 16 v ddext current in hibernate state v ddext = 3.60 v, clkin=0 mhz, t j =maximum, with voltage regulator off (v ddint =0 v) 50 100 50 100 a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 20 a i dddeepsleep 15 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk =0 mhz table 16 table 15 ma i ddsleep 15, 17 v ddint current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz i dddeepsleep + (0.14 v ddint f sclk ) i dddeepsleep + (0.14 v ddint f sclk ) ma i ddint 18 v ddint current f cclk > 0 mhz, f sclk > 0 mhz i ddsleep + ( table 18 asf) i ddsleep + ( table 18 asf) ma 1 applies to all 300 mhz and 40 0 mhz speed grade models. see ordering guide on page 68 . 2 applies to all 500 mhz, 533 mhz, and 600 mhz speed grade models. see ordering guide on page 68 . 3 applies to all output and bidirectional pins except port f pins, port g pins, and port h pins. 4 applies to port f pins pf7C0. 5 applies to port f pins pf15C8, all port g pins, and all port h pins. 6 maximum combined curre nt for port f7C0. 7 maximum total current for all port f, port g, and port h pins. 8 applies to all input pins except pj4. 9 applies to input pin pj4 only. 10 applies to jtag input pins (tck, tdi, tms, trst ). 11 applies to three-statable pins. 12 applies to bidirectional pins pj2 and pj3. 13 applies to all signal pins. 14 guaranteed, but not tested. 15 see the adsp-bf537 blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 16 clkin must be tied to v ddext or gnd during hibernate. 17 in the equations, the f sclk parameter is the system clock in mhz. 18 see table 17 for the list of i ddint power vectors covered. 300 mhz/400 mhz 1 500 mhz/533 mhz/600 mhz 2 parameter test conditions min typ max min typ max unit
rev. i | page 28 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 system designers should refer to estimating power for the ADSP-BF534/bf536/bf537 blackfin processors (ee-297) , which provides detailed information for optimizing designs for lowest power. all topics discussed in this section are described in detail in ee-297. total power dissi pation has two components: 1. static, including leakage current 2. dynamic, due to transistor switchin g characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 26 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 16 or table 15 ), and i ddint specifies the total power specific ation for the listed test condi- tions, including the dynamic comp onent as a function of voltage (v ddint ) and frequency ( table 18 ). the dynamic component is also su bject to an activity scaling factor (asf) which represents ap plication code running on the processor ( table 17 ). table 15. static currentC500 mhz, 533 mhz, and 600 mhz speed grade devices (ma) 1 t j (c) voltage (v ddint ) 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v 1.43 v C40 3.9 4.7 6.8 8.2 9.9 12.0 14.6 17.3 20.3 24.1 27.1 28.6 36.3 44.4 0 17.0 19.2 21.9 25.0 28.2 32.1 36.9 41.8 47.7 53.8 61.0 63.8 73.2 84.1 25 35.0 39.2 44.3 50.8 56.1 63.3 69.1 76.4 84.7 93.5 104.5 109.1 123.4 138.8 40 53.0 59.2 65.3 71.9 79.1 88.0 96.6 108.0 120.0 130.7 142.6 148.5 166.5 185.6 55 76.7 84.6 93.6 103.1 113.7 123.9 136.3 148.3 162.8 178.4 194.4 201.4 223.7 247.5 70 110.1 120.0 130.9 142.2 156.5 171.3 185.2 201.7 220.6 239.7 259.8 268.8 295.9 325.2 85 150.1 164.5 178.7 193.2 210.4 228.9 247.7 268.8 291.4 314.1 341.1 351.2 384.6 420.3 100 202.3 219.2 236.5 255.8 277.8 299.8 323.8 351.2 378.8 407.5 440.4 453.4 494.3 538.2 105 223.8 241.4 260.4 282.0 303.4 328.7 354.5 381.7 410.8 443.6 477.8 492.2 535.1 581.5 1 values are guaranteed maximum i dddeepsleep specifications. table 16. static currentC300 mhz and 400 mhz speed grade devices (ma) 1 t j (c) voltage (v ddint ) 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v C40 2.6 3.2 3.7 4.5 5.5 6.6 7.9 9.3 10.5 12.5 13.9 14.8 0 6.6 7.8 8.4 9.9 10.912.313.815.517.519.621.723.1 25 12.2 13.5 14.8 16.4 18.2 19.9 22.7 25.6 28.4 31.8 35.7 37.2 40 17.2 19.0 20.6 22.9 25.9 28.2 31.6 34.9 38.9 42.9 47.6 49.5 55 25.7 27.8 30.9 33.7 37.3 41.4 44.8 50.0 54.8 59.4 66.1 68.4 70 37.6 41.3 44.8 48.9 53.9 58.6 63.9 69.7 76.9 84.0 92.2 94.9 85 53.7 58.3 63.7 69.0 75.9 82.9 90.5 98.4 106.4 115.3 124.6 128.1 100 75.1 82.3 88.5 95.8 104.0 112.5 121.8 130.6 141.3 153.2 164.8 169.7 105 84.5 91.2 98.2 106.0 114.2 123.0 132.4 143.3 155.0 167.4 179.8 185.4 115 2 103.8 111.8 120.3 127.6 138.0 148.5 159.6 171.4 184.6 198.8 213.4 219.6 120 2 115.5 123.6 132.2 141.9 152.3 163.7 175.6 189.3 202.8 217.7 232.3 238.6 1 values are guaranteed maximum i dddeepsleep specifications. 2 applies to automotive grade models only.
ADSP-BF534/adsp-bf536/adsp-bf537 rev. i | page 29 of 68 | july 2010 table 17. activity scaling factors i ddint power vector 1 activity scaling factor (asf) 2 i dd-peak 1.33 i dd-high 1.29 i dd-typ 1.00 i dd-app 0.88 i dd-nop 0.72 i dd-idle 0.43 1 see ee-297 for power vector definitions. 2 all asf values determined using a 10:1 cclk:sclk ratio. table 18. dynamic current (ma, with asf = 1.0) 1 frequency (mhz) voltage (v ddint ) 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v 1.43 v 50 11.0 13.7 19.13 18.2 18.67 19.13 19.6 21.2 24.1 25.5 28.5 28.6 28.85 29.2 100 27.922.730.828.429.330.832.935.337.840.643.543.744.1 45.8 200 36.942.655.049.251.555.058.362.967.069.773.074.075.7 80.7 300 n/a 61.5 79.2 70.4 74.6 79.2 84.4 90.7 94.3 99.1 103.9 105.5 108.0 113.4 400 n/a n/a n/a 92.4 97.2 104.3 109.8 116.5 121.9 128.0 134.6 136.6 139.8 145.1 500 n/a n/a n/a n/a n/a n/a n/a 142.3 149.3 157.5 164.7 166.7 169.8 176.9 533 n/a n/a n/a n/a n/a n/a n/a n/a 158.6 167.0 174.3 176.6 180.1 187.9 600 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 193.7 196.5 200.7 210.0 1 the values are not guaranteed as stand-alon e maximum specifications, they must be combined with static current per the equation s of electrical characteristics on page 26 .
rev. i | page 30 of 68 | july 2010 ADSP-BF534/adsp-bf536/adsp-bf537 absolute maximum ratings stresses greater than those listed in table 19 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 8 and table 21 provide details about the package branding for the blackfin processors. for a complete listing of product availability, see ordering guide on page 68 . table 19. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint ) C0.3 v to +1.43 v external (i/o) supply voltage (v ddext )C0.3 v to +3.8 v input voltage 1 1 applies only when v ddext is within specifications. when v ddext is outside speci- fications, the range is v ddext 0.2 v. C0.5 v to +3.6 v input voltage 1, 2 2 applies to 5 v tolerant pins scl, sda, and pj4. for duty cycles, see table 20 . C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext + 0.5 v storage temperature range C65 c to +150 c junction temperature while biased +125 c table 20. maximum duty cycle for input 1 transient voltage 1 applies to all signal pins with the ex ception of clkin, xtal, and vrout1C0. v in min (v) 2 v in max (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case ob served value must fall within one of the voltages specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. this is equivalent to the measured durati on of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.50 +3.80 100% C0.70 +4.00 40% C0.80 +4.10 25% C0.90 +4.20 15% C1.00 +4.30 10% esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. figure 8. product information on package table 21. package brand information 1 1 nonautomotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppzccc adsp-bf53x a yyww country_of_origin b
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 31 of 68 | jul y 2010 timing specifications component specifications are subject to change without notice. clock and reset timing table 22. clock input and reset timing p ara m eter m i nm a xun it timing requirement s t c kin c lkin p eriod 1, 2, 3, 4 1 combinations of the clkin frequency and the p ll clock multiplier must not exceed the allowed f vco , f cclk , and f sclk settings discussed in table 10 through table 14 . since by default the pll is multiplying the clki n frequency by 10, 300 mhz and 400 mhz speed grade parts can not use the full clkin p eriod range. 2 applies to pll bypass mode and pll non bypass mode. 3 clkin frequency must not change on the fly. 4 if the df bit in the pll_ctl register is set, then the maximum t ckin period is 50 ns. 20 . 0100 . 0 ns t c kinl c lkin l ow pul se 8 .0 ns t c kinh c lkin h igh pul se 8 .0 ns t bufd l a y c lkin to c lkbuf de l ay 10 ns t wr s t re s et asserted pul se w idth l ow 11 t c kin ns t noboot re s et deassertion to f irst ex terna l access de l ay 5 5 applies when processor is configured in no boot mode (bmode2-0 = b#000). 3 t c kin 5 t c kin ns figure 9. clock and reset timing table 23. power-up reset timing p ara m eter m i nm a xu n it timing requirement s t r s t_in_pwr re s et deasserted after the v dd int , v dd ext , v dd rt c , and c lkin p ins are stab l e and w ithin specification 3500 t c kin ns i n f ig u re 10 , v dd_ s upplie s is v dd int , v dd ext , v ddrt c figure 10. power -up reset timing clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset cb bt reset rstwr c ddses
r e v . i|p age 32 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 asynchronous memory read cycle timing table 24. asynchronous memory read cycle timing p ara m eter m i nm a xun it timing requirements t sda t da t a 15C0 set u p b efore c lkout 2 .1 ns t hda t da t a 15C0 h o l d after c lkout 0 .8 ns t sa r d y a r d y set u p b efore c lkout 4 .0 ns t ha r d y a r d y h o l d after c lkout 0 .0 ns switching characteristic s t d o ou tp u t de l ay after c lkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . 6 .0 ns t ho ou tp u t h o l d after c lkout 1 0 .8 ns figure 11. asynchronous memory read cycle timing t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t hardy t sardy t sdat t hdat t sardy clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 33 of 68 | jul y 2010 asynchronous memory write cycle timing table 25. asynchronous memory write cycle timing p ara m eter m i nm a xun it timing requirements t sa r d y a r d y set u p b efore c lkout 4 .0 ns t ha r d y a r d y h o l d after c lkout 0 .0 ns switching characteristic s t dda t da t a 15C0 disab l e after c lkout 6 .0 ns t en da t da t a 15C0 e nab l e after c lkout 1 .0 ns t d o ou tp u t de l ay after c lkout 1 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe, awe . 6 .0 ns t ho ou tp u t h o l d after c lkout 1 0 .8 ns figure 12. asynchronous memory write cycle timing setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe ardy data 15C0 t sardy t sardy t ddat t endat t hardy t ho t do t hardy
r e v . i|p age 34 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 external port bus request and grant cycle timing table 26 and figure 13 describe external port bus request and bus grant operations. table 26. external port bus request and grant cycle timing p ara m eter 1, 2 m i nm a xun it timing requirements t b s br asserted to c lkout l ow set u p 4 .6 ns t bh c lkout l ow to br deasserted h o l d t ime 0 .0 ns switching characteristics t sd c lkout l ow to a m s x , address , and a re / a we disab l e 4 .5 ns t s e c lkout l ow to a m s x , address , and a re / a we e nab l e 4 .5 ns t d bg c lkout h igh to bg asserted set u p 3 .6 ns t ebg c lkout h igh to bg deasserted h o l d t ime 3 .6 ns t d bh c lkout h igh to bgh asserted set u p 3 .6 ns t ebh c lkout h igh to bgh deasserted h o l d t ime 3 .6 ns 1 these timing parameters are based on worst-case operating conditions. 2 the pad loads for these timing parameters are 20 pf. figure 13. external port bus request and grant cycle timing amsx clkout bg bgh br addr 19-1 abe1-0 t bh t bs t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 35 of 68 | jul y 2010 sdram interface timing table 27. sdram interface timing p ara m eter m i nm a xun it timing requirement s t ssda t da t a 15C0 set u p b efore c lkout 1 .5 ns t h sda t da t a 15C0 h o l d after c lkout 0 .8 ns switching characteristics t dcad c omm a n d 1 , add r19C1, da t a 15C0 de l ay after c lkout 1 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 4 .0 ns t hcad c omm a n d 1 , add r19C1, da t a 15C0 h o l d after c lkout 1 .0 ns t dsda t da t a 15C0 disab l e after c lkout 6 .0 ns t en sda t da t a 15C0 e nab l e after c lkout 0 .5 ns t sc lk 2 2 these limits are specific to the sdram interface only. in addition, clkout must always comply with the limits in table 14 on page 25 . c lkout p eriod when t j +105 c 7 .5 ns t sc lk 2 c lkout p eriod when t j +105 c 10 ns t sc lkh c lkout w idth h igh 2 .5 ns t sc lkl c lkout w idth l ow 2 .5 ns figure 14. sdram interface timing t sclk clkout t sclkl t sclkh t ssdat t hsdat t ensdat t dcad t dsdat t hcad t dcad t hcad data (in) data (out) command, address (out) note: command = sras, scas, swe, sdqm, sms, sa10, scke.
r e v . i|p age 36 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 external dma request timing table 28 and figure 15 describe the external dma request operations. table 28. external dma request timing p ara m eter m i nm a xun it timing requirements t d r d m a rx asserted to c lkout h igh set u p 6 .0 ns t d h c lkout h igh to d m a rx deasserted h o l d t ime 0 .0 ns t d m a r ac t d m a rx acti v e pul se w idth 1 .0 t sc lk ns t d m a rin ac t d m a rx i nacti v e pul se w idth 1 .75 t sc lk ns figure 15. external dma request timing clkout t dr dmar0/1 (active low) t dh dmar0/1 (active high) t dmaract t dmarinact t dmarinact t dmaract
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 37 of 68 | jul y 2010 parallel peripheral interface timing table 29 and figure 16 on page 37 , figure 20 on page 40 , and figure 23 on page 42 describe parallel peripheral interface operations. table 29. parallel peripheral interface timing p ara m eter m i nm a xun it timing requirements t p c lkw ppi_ clk w idth 1 6 .0 ns t p c lk ppi_ clk p eriod 1 15 . 0 ns timing requirementsgp input and frame capture modes t s f s pe ex terna l f rame sync set u p b efore ppi_ c lk 6 .7 ns t hf s pe ex terna l f rame sync h o l d after ppi_ clk 1 .0 ns t sd rpe r ecei v e data set u p b efore ppi_ c lk 3 .5 ns t hd rpe r ecei v e data h o l d after ppi_ clk 1 .5 ns switching characteristicsgp output and frame capture modes t d f s pe i nterna l f rame sync de l ay after ppi_ c lk 8 .0 ns t hof s pe i nterna l f rame sync h o l d after ppi_ clk 1.7 ns t dd tpe t ransmit data de l ay after ppi_ c lk 8 .0 ns t hd tpe t ransmit data h o l d after ppi_ clk 1.8 ns 1 ppi_clk frequency cannot exceed f sclk /2. figure 16. ppi gp rx mode with internal frame sync timing figure 17. ppi gp rx mode with external frame sync timing t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw
r e v . i|p age 38 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 18. ppi gp tx mode with internal frame sync timing figure 19. ppi gp tx mode with external frame sync timing t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 39 of 68 | jul y 2010 serial port timing table 30 through table 33 on page 42 and figure 20 on page 40 through figure 23 on page 42 describe serial port operations. table 30. serial portsexternal clock p ara m eter m i nm a xun it timing requirements t s f s e tf s x/rf s x set u p b efore t sc lkx/r sc lkx 1 3 .0 ns t hf s e tf s x/rf s x h o l d after t sc lkx/r sc lkx 1 3 .0 ns t sd re r ecei v e data set u p b efore r sc lkx 1 3 .0 ns t sc lkew t sc lkx/r sc lkx w idth 4 .54 .5 t sc lke t sc lkx/r sc lkx p eriod 15 . 015 . 0 t s u d te start -up de l ay f rom s port e nabl e t o f irst ex terna l tf sx 2 4 .0 t sc lke ns t s u d re start -up de l ay f rom s port e nabl e t o f irst ex terna l rfsx 2 4 .0 t sc lke ns switching characteristics t d f s e tf s x/rf s x de l ay after t sclkx/r sc lk (i nterna lly g enerated tf s x/rf sx) 3 10 . 0 ns t hof s e tf s x/rf s x h o l d after t sc lkx/r sc lk (i nterna lly g enerated tf s x/rf s x) 2 0 ns t dd te t ransmit data de l ay after t sc lkx 2 10 . 0 ns t hd te t ransmit data h o l d after t sc lkx 2 0 ns 1 referenced to sample edge. 2 verified in design but untested. after bein g enabled, the serial port requires exte rnal clock pulsesbefore the first external frame sync edgeto initia lize the serial port. 3 referenced to drive edge. table 31. serial portsinternal clock 2 . 25 v v dd ext < 2 . 70 v or 0 . 80 v v dd int < 0 .95 v 1 2 . 70 v v dd ext 3 .60 v a n d 0 . 95 v v dd int 1 . 43 v 2, 3 p ara m eter m i nm a xm i nm a xun it timing requirements t s f s i tf s x/rf sx set u p b efore t sc lkx/r sc lkx 4 8 . 58 . 0 ns t hf s i tf s x/rf sx h o l d after t sclkx/r sc lkx 4 C1 . 5C1 .5 ns t sd ri r ecei v e data set u p b efore r sc lkx 4 8 . 58 . 0 ns t hd ri r ecei v e data h o l d after r sclkx 4 C1 . 5C1 .5 ns switching characteristics t d f s i tf s x/rf sx de l ay after t sc lkx/r sc lkx (i nterna lly g enerated tf s x/rf sx) 5 3 . 03 . 0 ns t hof s i tf s x/rf sx h o l d after t sclkx/r sc lkx (i nterna lly g enerated tf s x/rf sx) 5 1 . 0 1 . 0 ns t dd ti t ransmit data de l ay after t sclkx 5 3 . 03 . 0 ns t hd ti t ransmit data h o l d after t sc lkx 5 1 . 0 1 . 0 ns t sc lkiw t sc lkx/r sclkx w idth 4 . 54 . 5 ns 1 applies to all nonautomotive-grade devices when operated within either of these voltage ranges. 2 applies to all nonautomotive-grade devices wh en operated within these voltage ranges. 3 all automotive-grade devices are within these specifications. 4 referenced to sample edge. 5 referenced to drive edge.
r e v . i|p age 40 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 20. serial ports figure 21. serial port start up with external clock and frame sync t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 41 of 68 | jul y 2010 table 32. serial portsenable and three-state p ara m eter m i nm a xun it switching characteristics t d tene data e nab l e de l ay from ex terna l t sc lkx 1 0 ns t dd tte data disab l e de l ay from ex terna l t sc lkx 1 10 . 0 ns t d teni data e nab l e de l ay from i nterna l t sc lkx 1 C2 . 0 ns t dd tti data disab l e de l ay from i nterna l t sc lkx 1 3 .0 ns 1 referenced to drive edge. figure 22. enable and three-state tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
r e v . i|p age 42 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 table 33. external late frame sync p ara m eter m i nm a xun it switching characteristics t dd tlf s e data de l ay from l ate ex terna l tf s x or ex terna l rf s x with m c men = 1, mf d = 0 1, 2 10 . 0 ns t d tenlf s data e nab l e from l ate f s or m c men = 1, mf d = 0 1, 2 0 ns 1 mcmen = 1, tfsx enable and tfsx valid follow t ddtenfs and t ddtlfs . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2, then t ddte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfs apply. figure 23. external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 43 of 68 | jul y 2010 serial peripheral interface portmaster timing table 34 and figure 24 describe spi port master operations. table 34. serial peripheral interface (spi) portmaster timing 2 .25 v v dd ext < 2. 70 v or 0 .80 v v dd int < 0 . 95 v 1 2 .70 v v dd ext 3. 60 v a n d 0 . 95 v v dd int 1 . 43 v 2, 3 p ara m eter m i nm a xm i nm a xun it iieireets t ss pi d m data i np u t v a l id to sck e dge ( data i np u t set u p )8 .77 .5 ns t hs pi d m sck samp l ing e dge to data i np u t i n v a l id C1 . 5C 1 . 5 ns switchingcharacteristics t sdsc im s pi s elx l ow to f irst sck e dge 2 t sc lk C1 . 52 t sc lk C1 . 5 ns t s pi c hm seria l cl ock h igh p eriod 2 t sc lk C1 . 52 t sc lk C1 . 5 ns t s pi c lm seria l cl ock l ow p eriod 2 t sc lk C1 . 52 t sc lk C1 . 5 ns t s pi c lk seria l cl ock p eriod 4 t sc lk C1 . 54 t sc lk C1 . 5 ns t hds m l ast sc k e dge to spi s elx h igh 2 t sc lk C1 . 52 t sc lk C1 . 5 ns t s pit d m se qu entia l t ransfer de l ay 2 t sc lk C1 . 52 t sc lk C1 .5 ns t dds pi d m sck e dge to data ou t v a l id ( data ou t de l ay )6 6 ns t hds pi d m sck e dge to data ou t i n v a l id ( data ou t h o l d )C1 . 0C1 . 0 ns 1 applies to all nonautomotive-grade devices when operated within either of these voltage ranges. 2 applies to all nonautomotive-grade devices wh en operated within these voltage ranges. 3 all automotive-grade devices are within these specifications. figure 24. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely p spixs p spixsi p spixis ip spixsi p spixis ip p p spi spi sspi spi spi
r e v . i|p age 44 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 serial peripheral interface portslave timing table 35 and figure 25 describe spi port slave operations. table 35. serial peripheral interface (spi) portslave timing p ara m eter m i nm a xun it timing requirements t s pi c h s seria l cl ock h igh p eriod 2 t sc lk C1 .5 ns t s pi c l s seria l cl ock low p eriod 2 t sc lk C1 .5 ns t s pi c lk seria l cl ock p eriod 4 t sc lk ns t hds l ast sc k e dge to spi ss n ot asserted 2 t sc lk C1 .5 ns t s pit ds se qu entia l t ransfer de l ay 2 t sc lk C1 .5 ns t sdsc i s pi ss assertion to f irst sc k e dge 2 t sc lk C1 . 5 ns t ss pi d data i np u t v a l id to sc k e dge ( data i np u t set u p )1 .6 ns t hs pi d sck samp l ing e dge to data i np u t i n v a l id 1 .6 ns switching characteristics t ds oe s pi ss assertion to data ou t acti v e 08ns t dsd hi s pi ss deassertion to data h igh i mpedance 08ns t dds pi d sck e dge to data ou t v a l id ( data ou t de l ay )1 0 ns t hds pi d sck e dge to data ou t i n v a l id ( data ou t h o l d )0 ns figure 25. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 45 of 68 | jul y 2010 general-purpose port timing table 36 and figure 26 describe general-purpose port operations. universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-bf537 blackfin processor hardware reference . table 36. general-purpose port timing p ara m eter m i nm a xun it iieireet t wfi g enera l-pu rpose p ort p in i np u t pul se w idth t sc lk + 1 ns switchingcharacteristic t gpo d g enera l-pu rpose p ort p in ou tp u t de l ay from c lkout l ow 06ns igre. enerarposeortiming c t wfi t gpod
r e v . i|p age 46 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 timer clock timing table 37 and figure 27 describe timer clock timing. timer cycle timing table 38 and figure 28 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 37. timer clock timing p ara m eter m i nm a xun it switching characteristic t to d p t imer ou tp u t u pdate de l ay after ppi_ c lk h igh 12 ns figure 27. timer clock timing ppi_clk tmrx output t todp table 38. timer cycle timing 2 .25 v v dd ext < 2 . 70 v or 0 .80 v v dd int < 0 . 95 v 1 2 . 70 v v dd ext 3 . 60 v a n d 0 . 95 v v dd int 1 . 43 v 2, 3 p ara m eter m i nm a xm i nm a xun it timing characteristics t wl t imer pul se w idth i np u t l ow (m eas u red i n sc lk cyc l es ) 4 1 t sc lk 1 t sc lk ns t wh t imer pul se w idth i np u t h igh (m eas u red i n sclk cyc l es ) 4 1 t sc lk 1 t sc lk ns t ti s t imer i np u t set u p t ime b efore c lkout l ow 5 5 .55 .0 ns t tih t imer i np u t h o l d t ime after c lkout l ow 5 1 .51 .5 ns switching characteristics t hto t imer pul se w idth ou tp u t (m eas u red i n sc lk cyc l es )1 t sc lk (2 32 C1) t sc lk 1 t sc lk (2 32 C1) t sc lk ns t to d t imer ou tp u t u pdate de l ay after c lkout h igh 6 .56 . 0 ns 1 applies to all nonautomotive-grade devices when operated within either of these voltage ranges. 2 applies to all nonautomotive-grade devices wh en operated within these voltage ranges. 3 all automotive-grade devices are within these specifications. 4 the minimum pulse widths apply for tmrx sign als in width capture and external clock modes. they also apply to the pf15 or ppi_c lk signals in pwm output mode. 5 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 28. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh t wl t tod t hto
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 47 of 68 | jul y 2010 jtag test and emulation port timing table 39 and figure 29 describe jtag port operations. table 39. jtag port timing p ara m eter m i nm a xun it timing parameters t t c k t ck p eriod 20 ns t s t a p t d i, tm s set u p b efore t c k h igh 4 ns t ht a p t d i, tm s h o l d after t c k h igh 4 ns t ss y s system i np u ts set u p b efore t c k h igh 1 4 ns t hs y s system i np u ts h o l d after t ck h igh 1 5 ns t tr s tw tr s t pul se w idth 2 (m eas u red in t c k cyc l es )4t c k switching characteristics t d t d o t d o de l ay f rom t ck l ow 10 ns t ds y s system ou tp u ts de l ay after t c k l ow 3 01 2 ns 1 system inputs = data15C0, br , ardy, scl, sda, tfs0, tsclk0, rs clk0, rfs0, dr0pri, dr0sec, pf15C0, pg15C0, ph15C0, mdio, tck, trst , reset , nmi , rtxi, bmode2C0. 2 50 mhz maximum 3 system outputs = data15C0, addr19C1, abe1C0 , bg , bgh , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, mdc, mdio, tsclk0, tfs0, rfs0, rsclk0, dt0pri, dt0sec , pf15C0, pg15C0, ph15C0, rtxo, tdo, emu , xtal, vrout1C0. figure 29. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
r e v . i|p age 48 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 10/100 ethernet mac controller timing table 40 through table 45 and figure 30 through figure 35 describe the 10/100 ethernet ma c controller operations. this feature is only available on the adsp-bf536 and adsp-bf537 processors. table 40. 10/100 ethernet mac controll er timing: mii receive signal p ara m eter 1 m i nm a xun it f erx c lk erx c lk f re qu ency ( f sc lk = sclk f re qu ency )n one 25 + 1% f sc lk + 1% mhz t erx c lkw erx c lk w idth ( t erx c lk = erxc lk p eriod ) t erx c lk 35% t erx c lk 65% ns t erx c lki s rx i np u t v a l id to erx clk r ising e dge ( data i n set u p )7 .5 ns t erx c lkih erx c lk r ising e dge to rx i np u t i n v a l id ( data i n h o l d )7 .5 ns 1 mii inputs synchronous to erxclk are erxd3C0, erxdv, and erxer. table 41. 10/100 ethernet mac controll er timing: mii transmit signal p ara m eter 1 m i nm a xun it f etx c lk etx clk f re qu ency ( f sc lk = sclk f re qu ency )n one 25 + 1% f sc lk + 1% mhz t etx c lkw etx clk w idth ( t etx c lk = etx c lk p eriod ) t etx c lk 35% t etx c lk 65% ns t etx c lkov etx clk r ising e dge to tx ou tp u t v a l id ( data ou t v a l id )2 0 ns t etx c lkoh etx clk r ising e dge to tx ou tp u t i n v a l id ( data ou t h o l d )0 ns 1 mii outputs synchronous to etxclk are etxd3C0. table 42. 10/100 ethernet mac controller timing: rmii receive signal p ara m eter 1 m i nm a xun it f ref c lk ref_clk f requ ency ( f sc lk = sc lk f re qu ency )n one 50 + 1% 2 f sc lk + 1% mhz t ref c lkw ref_clk w idth ( t ref c lk = ref c lk p eriod ) t ref c lk 35% t ref c lk 65% ns t ref c lki s rx i np u t v a l id to rmii ref_ clk r ising e dge ( data i n set u p )4 ns t ref c lkih rmii ref_ c lk r ising e dge to rx i np u t i n v a l id ( data i n h o l d )2 ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. table 43. 10/100 ethernet mac controll er timing: rmii transmit signal p ara m eter 1 m i nm a xun it t ref c lkov rmii ref_ c lk r ising e dge to tx ou tp u t v a l id ( data ou t v a l id )7 .5 ns t ref c lkoh rmii ref_ c lk r ising e dge to tx ou tp u t i n v a l id ( data ou t h o l d )2 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0.
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 49 of 68 | jul y 2010 table 44. 10/100 ethernet mac controller timing: mii/rmii asynchronous signal p ara m eter 1, 2 m i nm a xun it t e c olh c ol pul se w idth h igh t etx c lk 1 . 5 t erx c lk 1 . 5 ns ns t e c oll c ol pul se w idth l ow t etx c lk 1 . 5 t erx c lk 1 . 5 ns ns t e c r s h c r s pul se w idth h igh t etx c lk 1 . 5 ns t e c r s l c r s pul se w idth l ow t etx c lk 1 . 5 ns 1 mii/rmii asynchronous signals are col, crs. these signals are applicable in both mii and rmii modes. the asynchronous col input is synchronized se parately to both the etxclk and the erxclk, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the t wo clocks. 2 the asynchronous crs input is synchronized to the etxclk, and mus t have a minimum pulse width high or low at least 1.5 times th e period of etxclk. table 45. 10/100 ethernet mac controller timing: mii station management p ara m eter 1 m i nm a xun it t m d io s m d io i np u t v a l id to m dc r ising e dge ( set u p )10 ns t m dc ih m dc r ising e dge to m d io i np u t i n v a l id (h o l d )10 ns t m dc ov m dc f a ll ing e dge to m d io ou tp u t v a l id 25 ns t m dc oh m dc f a ll ing e dge to m d io ou tp u t i n v a l id (h o l d )C1 ns 1 mdc/mdio is a 2-wire serial bidirectional port for controlling one or more external phys. mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk. mdio is a bidirectional data line. figure 30. 10/100 ethernet mac controller timing: mii receive signal figure 31. 10/100 ethernet mac controller timing: mii transmit signal t erxclkis t erxclkih erxd3C0 erxdv erxer erx_clk t erxclkw t erxclk t etxclkoh etxd3C0 etxen miitxclk t etxclk t etxclkov t etxclkw
r e v . i|p age 50 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 32. 10/100 ethernet mac controller timing: rmii receive signal figure 33. 10/100 ethernet mac controller timing: rmii transmit signal figure 34. 10/100 ethernet mac controller timing: asynchronous signal figure 35. 10/100 ethernet mac contro ller timing: mii station management t refclkis t refclkih erxd1C0 erxdv erxer rmii_ref_clk t refclkw t refclk t refclkov t refclkoh rmii_ref_clk etxd1C0 etxen t refclk miicrs, col t ecrsh t ecolh t ecrsl t ecoll mdio (input) mdio (output) mdc (output) t mdios t mdcoh t mdcih t mdcov
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 51 of 68 | jul y 2010 output d rive currents figure 36 through figure 47 show typical current-voltage char- acteristics for the output drivers of the processors. the curves represent the current drive capability of the output drivers as a function of output voltage. see table 9 on page 20 for informa- tion about which driver type co rresponds to a particular pin. figure 36. drive current a (low v ddext ) figure 37. drive current a (high v ddext ) figure 38. drive current b (low v ddext ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 100 60 40 -80 -60 -40 -20 120 20 80 - 100 v ddext = 2.25v @ 95 c v ddext = 2.50v @ 25 c v ddext = 2.75v @ - 40 c v ol v oh 0 s ou r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 150 100 50 - 150 - 100 - 50 v ol v oh 4.0 v ddext = 3.0v @ 95c v ddext = 3.3v @ 25c v ddext =3.6v@ - 40c 0 s o u r c e c u r r en t ( m a ) source voltage (v) 00 . 51 . 01 . 52 . 02 . 53 . 0 150 100 - 150 v ol v oh - 100 - 50 50 v ddext =2.25v@95c v ddext =2.50v@25c v ddext =2.75v@ - 40c figure 39. drive current b (high v ddext ) figure 40. drive current c (low v ddext ) figure 41. drive current c (high v ddext ) 0 s ou r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 150 100 50 - 200 - 150 v ol v oh 4.0 - 100 - 50 200 v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40c 0 s o ur c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 80 60 - 60 v ol v oh - 40 - 20 40 20 v ddext = 2.25v @ 95c v ddext = 2.50v @ 25c v ddext =2.75v@ - 40c 0 s ou r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 80 60 40 - 80 - 60 v ol v oh 4.0 - 40 - 20 100 20 v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40c
r e v . i|p age 52 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 42. drive current d (low v ddext ) figure 43. drive current d (high v ddext ) figure 44. drive current e (low v ddext ) 0 s ou r c e cu rr e nt (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 80 60 40 - 80 - 60 v ol v oh - 40 - 20 100 20 v ddext =2.25v@95c v ddext =2.50v@25c v ddext =2.75v@ - 40c 0 s o ur c e c ur r en t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 50 - 150 v ol v oh 4.0 - 100 - 50 150 v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40c 0 s o u r c e cu r r en t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 40 20 10 - 40 - 30 v ol v oh v ddext = 2.25v @ 95c v ddext = 2.50v @ 25c v ddext =2.75v@ - 40c - 20 - 10 50 30 - 50 figure 45. drive current e (high v ddext ) figure 46. drive current f (low v ddext ) figure 47. drive current f (high v ddext ) 0 s o ur c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 80 60 40 - 80 - 60 v ol v oh v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40c 4.0 - 40 - 20 20 - 40 s o u r c e c u rr e n t (m a ) source voltage (v) 00 . 51 . 01 . 52 . 02 . 53 . 0 - 60 0 - 10 v ol - 20 - 30 - 50 v ddext =2.25v@95c v ddext =2.50v@25c v ddext =2.75v@ - 40c - 40 s o ur c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 - 10 - 20 - 80 - 70 v ol 4.0 - 60 - 50 - 30 v ddext =3.0v@95c v ddext =3.3v@25c v ddext =3.6v@ - 40c
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 53 of 68 | jul y 2010 test con d itions all timing parameters appearing in this data sheet were measured under the conditions described in this section. figure 48 shows the measurement po int for ac measurements (other than output enable/disable). the measurement point is v meas = v ddext /2. output enable time output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure 49 ). the time t ena_measured is the interval from wh en the reference signal switches to when the output voltage reaches 2.0 v (output high) or 1.0 v (output low). time t trip is the interval from when the output starts driving to when the output reaches the 1.0 v or 2.0 v trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the da ta bus) are enabled, the measure- ment value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l , and the load current, i l . this decay time ca n be approximated by the equation: the output disable time t dis is the difference between t dis_measured and t decay as shown in figure 49 . the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the mea- sured output-high or output-low voltage. the time t decay is calculated with the test loads c l and i l , and with v equal to 0.5 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. a typical v is 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three-state current (per data line). the hold time is t decay plus the minimum disable time (for example, t dsdat for an sdram write cycle). figure 48. voltage reference levels for ac measurements (except output enable/disable) input or output v meas v meas t ena t ena_measured t trip ? = figure 49. output enable/disable t decay c l v () ? = reference signal t dis output starts driving v oh (measured)
r e v . i|p age 54 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 capacitive loading output delays and holds are based on standard capa citive loads: 30 pf on all pins (see figure 50 ). figure 51 through figure 60 on page 56 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 50. equivalent device loading for ac measurements (includes all fixtures) t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 figure 51. typical output dela y or hold for driver a at v ddext min figure 52. typical output delay or hold for driver a at v ddext max load capacitance (pf) rise time rise and fall time ns (10%t o 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10 % to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 55 of 68 | jul y 2010 figure 53. typical output delay or hold for driver b at v ddext min figure 54. typical output delay or hold for driver b at v ddext max figure 55. typical output delay or hold for driver c at v ddext min load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 25 30 20 15 10 5 0 0 50 100 150 200 250 fall time figure 56. typical output delay or hold for driver c at v ddext max figure 57. typical output delay or hold for driver d at v ddext min figure 58. typical output delay or hold for driver d at v ddext max load capacitance (pf) rise time rise and fall time ns (10% to 90%) 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and f all time ns (10 % to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
r e v . i|p age 56 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 59. typical output dela y or hold for driver e at v ddext min figure 60. typical output dela y or hold for driver e at v ddext max load capacitance (pf) rise time rise and fall time ns (10% to 90%) 36 32 28 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 36 32 28 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time figure 61. typical output delay or hold for driver f at v ddext min figure 62. typical output delay or hold for driver f at v ddext max load capacitance (pf) rise time rise and fall time ns (10% to 90%) 36 32 28 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 36 32 28 24 20 16 12 8 4 0 0 50 100 150 200 250 fall time
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 57 of 68 | jul y 2010 thermal characteristics to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature ( c) t case = case temperature ( c) measured by customer at top center of package. jt = from table 46 p d = power dissipation (see the power dissipation discussion and the tables on page 28 for the method to calculate p d ). values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for package comparison and printed circuit board design considerations when an external heat sink is required. values of jb are provided for package comparison and printed circuit board design considerations. in table 46 through table 48 , airflow measurements comply with jedec standard s jesd51-2 and jesd51-6, and the junc- tion-to-board measurement comp lies with jesd51-8. test board and thermal via design comply with jedec standards jesd51-9 (bga). the junction-t o-case measurement complies with mil-std-883 (method 1012. 1). all measurements use a 2s2p jedec test board. industrial applications using the 208-ball bga package require thermal vias, to an embedded grou nd plane, in the pcb. refer to jedec standard jesd51-9 for pr inted circuit board thermal ball land and thermal vi a design information. t j t case jt p d () += t j t a ja p d () += table 46. thermal characteristics (182-ball bga) p ara m eter c o n ditio ntyp ical un it j a 0 l inear m / s airf l ow 32 . 80 c /w jm a 1 l inear m / s airf l ow 29 . 30 c /w jm a 2 l inear m / s airf l ow 28 . 00 c /w jb 20 . 10 c /w j c 7 .92 c /w jt 0 l inear m / s airf l ow 0 .19 c /w jt 1 l inear m / s airf l ow 0 .35 c /w jt 2 l inear m / s airf l ow 0 .45 c /w table 47. thermal characteristics (208-ball bga without thermal vias in pcb) p ara m eter c o n ditio ntyp ical un it j a 0 l inear m / s airf l ow 23 . 30 c /w jm a 1 l inear m / s airf l ow 20 . 20 c /w jm a 2 l inear m / s airf l ow 19 . 20 c /w jb 13 . 05 c /w j c 6 .92 c /w jt 0 l inear m / s airf l ow 0 .18 c /w jt 1 l inear m / s airf l ow 0 .27 c /w jt 2 l inear m / s airf l ow 0 .32 c /w table 48. thermal characteristics (208-ball bga with thermal vias in pcb) p ara m eter c o n ditio ntyp ical un it j a 0 l inear m / s airf l ow 22 . 60 c /w jm a 1 l inear m / s airf l ow 19 . 40 c /w jm a 2 l inear m / s airf l ow 18 . 40 c /w jb 13 . 20 c /w j c 6 .85 c /w jt 0 l inear m / s airf l ow 0 .16 c /w jt 1 l inear m / s airf l ow 0 .27 c /w jt 2 l inear m / s airf l ow 0 .32 c /w
r e v . i|p age 58 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 182-ball csp_bga ball assignment table 49 lists the csp_bga ball a ssignment by signal mne- monic. table 50 on page 59 lists the csp_bga ball assignment by ball number. table 49. 182-ball csp_bga ball assignment (alphabetically by signal mnemonic) mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. a be0 h13 c lkout b14 gnd l6 pg8 e3 s r as d 13 a be1 h12 da t a 0m9 gn d l8 pg9 e4 s we d 12 add r1 j14 da t a 1n9 gn d l10 ph0 c 2t c kp2 add r10 m13 da t a 10 n6 gn d m4 ph1 c 3t d im3 add r11 m14 da t a 11 p6 gn d m10 ph10 b6 t d on3 add r12 n14 da t a 12 m5 gn d p14 ph11 a 2tm s n2 add r13 n13 da t a 13 n5 nmi b10 ph12 a 3tr st n1 add r14 n12 da t a 14 p5 pf0 m1 ph13 a 4v dd ext a 1 add r15 m11 da t a 15 p4 pf1 l1 ph14 a 5v dd ext c 12 add r16 n11 da t a 2p9 pf10 j2 ph15 a 6v dd ext e6 add r17 p13 da t a 3m8 pf11 j3 ph2 c 4v dd ext e11 add r18 p12 da t a 4n8 pf12 h1 ph3 c 5v dd ext f4 add r19 p11 da t a 5p8 pf13 h2 ph4 c 6v dd ext f12 add r2 k14 da t a 6m7 pf14 h3 ph5 b1 v dd ext h5 add r3 l14 da t a 7n7 pf15 h4 ph6 b2 v dd ext h10 add r4 j13 da t a 8 p7 pf2 l2 ph7 b3 v dd ext j11 add r5 k13 da t a 9 m6 pf3 l3 ph8 b4 v dd ext j12 add r6 l13 emu m2 pf4 l4 ph9 b5 v dd ext k7 add r7 k12 gn da 10 pf5 k1 pj0 c 7v dd ext k9 add r8 l12 gn da 14 pf6 k2 pj1 b7 v dd ext l7 add r9 m12 gn dd 4pf7k3 pj10 d 10 v dd ext l9 a m s0 e14 gn d e7 pf8 k4 pj11 d 11 v dd ext l11 a m s1 f14 gn d e9 pf9 j1 pj2 b11 v dd ext p1 a m s2 f13 gn d f5 pg0 g1 pj3 c 11 v dd int e5 a m s3 g12 gn d f6 pg1 g2 pj4 d 7v dd int e8 a oe g13 gn d f10 pg10 d 1pj5 d 8v dd int e10 a r d ye13 gn d f11 pg11 d 2pj6 c 8v dd int g10 a re g14 gn d g4 pg12 d 3pj7b8 v dd int k5 a we h14 gn d g5 pg13 d 5pj8 d 9v dd int k8 bg p10 gn d g11 pg14 d 6pj9 c 9v dd int k10 bgh n10 gn d h11 pg15 c 1re set c 10 v ddrt c b9 bmo d e0 n4 gn d j4 pg2 g3 rtxo a 8vrout0 a 13 bmo d e1 p3 gn d j5 pg3 f1 rtxi a 9vrout1b12 bmo d e2 l5 gn d j9 pg4 f2 sa 10 e12 xt a l a 11 br d 14 gn d j10 pg5 f3 scas c 14 clkbuf a 7gn d k6 pg6 e1 sc ke b13 c lkin a 12 gn d k11 pg7 e2 s m s c 13
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 59 of 68 | jul y 2010 table 50. 182-ball csp_bga ball assignme nt (numerically by ball number) b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic a 1v dd ext c 10 re set f5 gn d j14 add r1 m9 da t a 0 a 2ph11 c 11 pj3 f6 gn d k1 pf5 m10 gn d a 3ph12 c 12 v dd ext f10 gn d k2 pf6 m11 add r15 a 4ph13 c13 sm s f11 gn d k3 pf7 m12 add r9 a 5ph14 c14 scas f12 v dd ext k4 pf8 m13 add r10 a 6ph15 d 1pg10f13 a m s 2 k5 v dd int m14 add r11 a 7 clkbuf d 2pg11f14 a m s 1 k6 gn d n1 tr st a 8rtxo d 3 pg12 g1 pg0 k7 v dd ext n2 tm s a 9rtxi d 4gn d g2 pg1 k8 v dd int n3 t d o a 10 gn dd 5 pg13 g3 pg2 k9 v dd ext n4 bmo d e0 a 11 xt a l d 6pg14g4gn d k10 v dd int n5 da t a 13 a 12 c lkin d 7 pj4 g5 gn d k11 gn d n6 da t a 10 a 13 vrout0 d 8pj5g10v dd int k12 add r7 n7 da t a 7 a 14 gn dd 9pj8g11gn d k13 add r5 n8 da t a 4 b1 ph5 d 10 pj10 g12 a m s 3 k14 add r2 n9 da t a 1 b2 ph6 d 11 pj11 g13 a oe l1 pf1 n10 bgh b3 ph7 d 12 swe g14 a re l2 pf2 n11 add r16 b4 ph8 d 13 sr as h1 pf12 l3 pf3 n12 add r14 b5 ph9 d 14 br h2 pf13 l4 pf4 n13 add r13 b6 ph10 e1 pg6 h3 pf14 l5 bmo d e2 n14 add r12 b7 pj1 e2 pg7 h4 pf15 l6 gn d p1 v dd ext b8 pj7 e3 pg8 h5 v dd ext l7 v dd ext p2 t c k b9 v dd rt c e4 pg9 h10 v dd ext l8 gn d p3 bmo d e1 b10 nmi e5 v dd int h11 gn d l9 v dd ext p4 da t a 15 b11 pj2 e6 v dd ext h12 a be1 l10 gn d p5 da t a 14 b12 vrout1 e7 gn d h13 a be0 l11 v dd ext p6 da t a 11 b13 sc ke e8 v dd int h14 a we l12 add r8 p7 da t a 8 b14 c lkout e9 gnd j1 pf9 l13 add r6 p8 da t a 5 c 1pg15e10v dd int j2 pf10 l14 add r3 p9 da t a 2 c 2ph0e11v dd ext j3 pf11 m1 pf0 p10 bg c 3ph1e12 sa 10 j4 gn d m2 emu p11 add r19 c 4ph2e13 a r d yj5 gn d m3 t d ip12 add r18 c 5ph3e14 a m s 0 j9 gn d m4 gn d p13 add r17 c 6ph4f1pg3j10gn d m5 da t a 12 p14 gn d c 7pj0f2pg4j11v dd ext m6 da t a 9 c 8pj6f3pg5j12v dd ext m7 da t a 6 c 9pj9f4v dd ext j13 add r4 m8 da t a 3
r e v . i|p age 60 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 figure 63 shows the top view of the csp_bga ball configuration. figure 64 shows the bottom view of the csp_bga ball configuration. figure 63. 182-ball csp_bga configuration (top view) a b c d e f g h j k l m n p 1234567891011121314 v ddint v ddext gnd i/o key: v rout v ddrtc figure 64. 182-ball csp_bga configuration (bottom view) a b c d e f g h j k l m n p 123456789 10 11 12 13 14 v ddint v ddext gnd i/o key: v rout v ddrtc
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 61 of 68 | jul y 2010 208-ball csp_bga ball assignment table 51 lists the csp_bga ball a ssignment by signal mne- monic. table 52 on page 62 lists the csp_bga ball assignment by ball number. table 51. 208-ball csp_bga ball assignment (alphabetically by signal mnemonic) mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. a be0 p19 da t a 12 y4 gn d m13 pg6 e2 t d iv1 a be1 p20 da t a 13 w4 gn d n9 pg7 d 1t d oy2 add r1 r19 da t a 14 y3 gn d n10 pg8 d 2tm s u2 add r10 w18 da t a 15 w3 gn d n11 pg9 c 1tr st u1 add r11 y18 da t a 2y9 gn d n12 ph0 b4 v dd ext g7 add r12 w17 da t a 3w9 gn d n13 ph1 a 5v dd ext g8 add r13 y17 da t a 4y8 gn d p11 ph10 b9 v dd ext g9 add r14 w16 da t a 5w8 gn d v2 ph11 a 10 v dd ext g10 add r15 y16 da t a 6y7 gn d w2 ph12 b10 v dd ext h7 add r16 w15 da t a 7w7 gn d w19 ph13 a 11 v dd ext h8 add r17 y15 da t a 8y6 gn d y1 ph14 b11 v dd ext j7 add r18 w14 da t a 9w6 gn d y13 ph15 a 12 v dd ext j8 add r19 y14 emu t1 gn d y20 ph2 b5 v dd ext k7 add r2 t20 gn da 1nmi c 20 ph3 a 6v dd ext k8 add r3 t19 gn da 13 pf0 t2 ph4 b6 v dd ext l7 add r4 u20 gn da 20 pf1 r1 ph5 a 7v dd ext l8 add r5 u19 gn d b2 pf10 l2 ph6 b7 v dd ext m7 add r6 v20 gn d g11 pf11 k1 ph7 a 8v dd ext m8 add r7 v19 gn d h9 pf12 k2 ph8 b8 v dd ext n7 add r8 w20 gn d h10 pf13 j1 ph9 a 9v dd ext n8 add r9 y19 gn d h11 pf14 j2 pj0 b12 v dd ext p7 a m s0 m20 gn d h12 pf15 h1 pj1 b13 v dd ext p8 a m s1 m19 gn d h13 pf2 r2 pj10 b19 v dd ext p9 a m s2 g20 gn d j9 pf3 p1 pj11 c 19 v dd ext p10 a m s3 g19 gn d j10 pf4 p2 pj2 d 19 v dd int g12 a oe n20 gn d j11 pf5 n1 pj3 e19 v dd int g13 a r d yj19 gn d j12 pf6 n2 pj4 b18 v dd int g14 a re n19 gn d j13 pf7 m1 pj5 a 19 v dd int h14 a we r20 gn d k9 pf8 m2 pj6 b15 v dd int j14 bg y11 gn d k10 pf9 l1 pj7 b16 v dd int k14 bgh y12 gn d k11 pg0 h2 pj8 b17 v dd int l14 bmo d e0 w13 gn d k12 pg1 g1 pj9 b20 v dd int m14 bmo d e1 w12 gn d k13 pg10 c 2re set d 20 v dd int n14 bmo d e2 w11 gn d l9 pg11 b1 rtxo a 15 v dd int p12 br f19 gn d l10 pg12 a 2rtxi a 14 v dd int p13 c lkbuf b14 gn d l11 pg13 a 3 sa 10 l20 v dd int p14 c lkin a 18 gn d l12 pg14 b3 scas k20 v ddrt c a 16 c lkout h19 gnd l13 pg15 a 4 sc ke h20 vrout0 e20 da t a 0y10 gn d m9 pg2 g2 s m s j20 vrout1 f20 da t a 1w10 gn d m10 pg3 f1 s r as k19 xt a l a 17 da t a 10 y5 gn d m11 pg4 f2 s we l19 da t a 11 w5 gn d m12 pg5 e1 t c kw1
r e v . i|p age 62 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 table 52 lists the csp_bga ball a ssignment by ball number. table 51 on page 61 lists the csp_bga ball assignment by sig- nal mnemonic. table 52. 208-ball csp_bga ball assignme nt (numerically by ball number) b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic b all n o. mne mo n ic a 1gn dc 19 pj11 j9 gn d m19 a m s 1 w1 t c k a 2pg12 c 20 nmi j10 gn d m20 a m s 0 w2 gn d a 3pg13 d 1pg7j11gn d n1 pf5 w3 da t a 15 a 4pg15 d 2pg8j12gn d n2 pf6 w4 da t a 13 a 5ph1 d 19 pj2 j13 gn d n7 v dd ext w5 da t a 11 a 6ph3 d 20 re set j14 v dd int n8 v dd ext w6 da t a 9 a 7 ph5 e1 pg5 j19 a r d yn9 gn d w7 da t a 7 a 8 ph7 e2 pg6 j20 s m s n10 gn d w8 da t a 5 a 9 ph9 e19 pj3 k1 pf11 n11 gn d w9 da t a 3 a 10 ph11 e20 vrout0 k2 pf12 n12 gn d w10 da t a 1 a 11 ph13 f1 pg3 k7 v dd ext n13 gn d w11 bmo d e2 a 12 ph15 f2 pg4 k8 v dd ext n14 v dd int w12 bmo d e1 a 13 gn d f19 br k9 gn d n19 a re w13 bmo d e0 a 14 rtxi f20 vrout1 k10 gn d n20 a oe w14 add r18 a 15 rtxo g1 pg1 k11 gn d p1 pf3 w15 add r16 a 16 v dd rt c g2 pg2 k12 gn d p2 pf4 w16 add r14 a 17 xt a lg7 v dd ext k13 gn d p7 v dd ext w17 add r12 a 18 c lkin g8 v dd ext k14 v dd int p8 v dd ext w18 add r10 a 19 pj5 g9 v dd ext k19 s r as p9 v dd ext w19 gn d a 20 gn d g10 v dd ext k20 scas p10 v dd ext w20 add r8 b1 pg11 g11 gn d l1 pf9 p11 gn d y1 gn d b2 gn d g12 v dd int l2 pf10 p12 v dd int y2 t d o b3 pg14 g13 v dd int l7 v dd ext p13 v dd int y3 da t a 14 b4 ph0 g14 v dd int l8 v dd ext p14 v dd int y4 da t a 12 b5 ph2 g19 a m s3 l9 gn d p19 a be0 y5 da t a 10 b6 ph4 g20 a m s2 l10 gn d p20 a be1 y6 da t a 8 b7 ph6 h1 pf15 l11 gn d r1 pf1 y7 da t a 6 b8 ph8 h2 pg0 l12 gn d r2 pf2 y8 da t a 4 b9 ph10 h7 v dd ext l13 gn d r19 add r1 y9 da t a 2 b10 ph12 h8 v dd ext l14 v dd int r20 a we y10 da t a 0 b11 ph14 h9 gn d l19 s we t1 emu y11 bg b12 pj0 h10 gn d l20 sa 10 t2 pf0 y12 bgh b13 pj1 h11 gn d m1 pf7 t19 add r3 y13 gn d b14 c lkbuf h12 gn d m2 pf8 t20 add r2 y14 add r19 b15 pj6 h13 gn d m7 v dd ext u1 tr st y15 add r17 b16 pj7 h14 v dd int m8 v dd ext u2 tm s y16 add r15 b17 pj8 h19 c lkout m9 gn d u19 add r5 y17 add r13 b18 pj4 h20 sc ke m10 gn d u20 add r4 y18 add r11 b19 pj10 j1 pf13 m11 gn d v1 t d iy19 add r9 b20 pj9 j2 pf14 m12 gn d v2 gn d y20 gn d c 1pg9j7 v dd ext m13 gn d v19 add r7 c 2pg10j8 v dd ext m14 v dd int v20 add r6
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 63 of 68 | jul y 2010 figure 65 shows the top view of the csp_bga ball configura- tion. figure 66 shows the bottom view of the csp_bga ball configuration. figure 65. 208-ball csp_bga configuration (top view) a b c d e f g h j k l m n p 1234567891011121314 1617181920 15 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y figure 66. 208-ball csp_bga configuration (bottom view) a b c d e f g h j k l m n p 20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 1 6 v ddint v ddext gnd i/o key: v rout v ddrtc r t u v w y
r e v . i|p age 64 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 outline dimensions dimensions in figure 67 and figure 68 are shown in millimeters. figure 67. 182-ball chip scale package ball grid array [csp_bga] (bc-182) dimensions shown in millimeters detail a detail a 0.50 0.45 0.40 1.31 1.21 1.10 a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 954 a1 corner index area top view bottom view 1.70 max 12.00 bsc sq (ball diameter) seating plane 0.25 min 0.12 coplanarity pin a1 indicator location notes: 0.80 bsc typ 1. compliant to jedec standard mo-205-ae, except for ball diameter. 2. center dimensions are nominal. 3. the actual position of the ball grid is within 0.15 of its ideal position relative to the package edges 10.40 bsc sq
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 65 of 68 | jul y 2010 figure 68. 208-ball chip scale package ball grid array [csp_bga] (bc-208-2) dimensions shown in millimeters * compliant to jedec standards mo-205-am with exception to package height and ball diameter. 0.80 bsc a b c d e f g h j k l m n p r t u v w y 15 14 17 16 19 18 20 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.20 bsc sq a1 corner index area coplanarity 0.12 detail a * 0.50 0.45 0.40 0.35 nom 0.30 min ball diameter top view a1 ball corner detail a seating plane 17.10 17.00 sq 16.90 * 1.75 1.61 1.46 1.36 1.26 1.16
r e v . i|p age 66 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 surface-mount d esign the following table is provided as an aid to pcb design. for industry-standard desi gn recommendations, refer to ipc-7351, generic requirements for surfac e mount design and land pat- tern standard . p ac k a g e p ac k a g e b all a ttach typ e p ac k a g e s older m as k op e n i ng p ac k a g e b all p ad s i z e 182-b a ll cs p_bg a (b c -182) so l der m ask defined 0 . 40 mm diameter 0 . 55 mm diameter 208-b a ll cs p_bg a (b c -208-2) so l der m ask defined 0 . 40 mm diameter 0 . 55 mm diameter
ADSP-BF534/adsp-bf536/adsp-bf537 r e v . i|p age 67 of 68 | jul y 2010 automotive pro d ucts the adbf534w model is availabl e with controlled manufactur- ing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models and designers should review the specifications section of this data sheet carefully. only the au tomotive grade products shown in table 53 are available for use in automotive applications. contact your local adi account representative for specific product ordering information and to obtain the specific auto- motive reliability reports for these models. table 53. automotive products p rod u ct f a m il y 1,2 t e mp erat u re r a ng e 3 sp eed g rade ( m a x ) p ac k a g e descri p tio n p ac k a g e op tio n ad bf534wbb c z4 a xx C40 c to +85 c 400 mhz 182-b a ll cs p_bg a b c -182 ad bf534wbb c z4bxx C40 c to +85 c 400 mhz 208-b a ll cs p_bg a b c -208-2 ad bf534wyb c z4bxx C40 c to +105 c 400 mhz 208-b a ll cs p_bg a b c -208-2 1 z = rohs compliant part. 2 xx denotes silicon revision. 3 referenced temperature is ambient temperature.
r e v . i|p age 68 of 68 | jul y 2010 ADSP-BF534/adsp-bf536/adsp-bf537 ? 2010 an alo g devices , in c. a ll ri g hts reserved. t rade m ark s an d reg istered trade mar k s are the p ro p ert y o f their res p ective o wn ers. d 05317-0-7/10 ( i ) or d ering gui d e in the following table csp_bga = ch ip scale package ball grid array. m odel 1 1 z = rohs compliant part. t e mp erat u re r a ng e 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 24 for junction temperature (t j ) specification which is the on ly temperature specification. sp eed g rade ( m a x ) p ac k a g e descri p tio n p ac k a g e op tio n ads p-bf534bb c -4 a C40 c to +85 c 400 mhz 182-b a ll cs p_bg a b c -182 ads p-bf534bb c z-4 a C40 c to +85 c 400 mhz 182-b a ll cs p_bg a b c -182 ads p-bf534bb c -5 a C40 c to +85 c 500 mhz 182-b a ll cs p_bg a b c -182 ads p-bf534bb c z-5 a C40 c to +85 c 50 0 mhz 1 8 2-b a ll cs p_bg a b c -182 ads p-bf534bb c z-4b C40 c to +85 c 400 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf534yb c z-4b C40 c to +105 c 400 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf534bb c z-5b C40 c to +85 c 500 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf536bb c -3 a C40 c to +85 c 300 mhz 182-b a ll cs p_bg a b c -182 ads p-bf536bb c z-3 a C40 c to +85 c 300 mhz 182-b a ll cs p_bg a b c-18 2 ads p- bf536bb c -4 a C40 c to +85 c 400 mhz 182-b a ll cs p_bg a b c -182 ads p-bf536bb c z-4 a C40 c to +85 c 400 mhz 182-b a ll cs p_bg a b c -182 ads p-bf536bb c z-3b C40 c to +85 c 300 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf536bb c z3brl C40 c to +85 c 300 mhz 208-b a ll cs p_bg a , 13" t ape and r eelb c -208-2 ads p-bf536bb c z-4b C40 c to +85 c 400 mhz 208-b a ll cs p_bg a b c-20 8-2 ads p- bf537bb c -5 a C40 c to +85 c 500 mhz 182-b a ll cs p_bg a b c -182 ads p-bf537bb c z-5 a C40 c to +85 c 500 mhz 182-b a ll cs p_bg a b c -182 ads p-bf537bb c z-5b C40 c to +85 c 500 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf537bb c z-5 a vC40 c to +85 c 533 mhz 182-b a ll cs p_bg a b c -182 ads p-bf537bb c z-5bv C40 c to +85 c 533 mhz 208-b a ll cs p_bg a b c -208-2 ads p-bf537kb c z-6 a v0 c to +70 c 600 mhz 1 82-b a ll cs p_bg a b c -182 ads p-bf537kb c z-6bv 0 c to +70 c 600 mhz 208-b a ll cs p_bg a b c -208-2

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